SpritesMind.Net

I found this in 32x docs (always nice to learn new things ;) ) http://gxdev.wordpress.com/files/2008/01/32x_vdp_hblank.gif http://gxdev.wordpress.com/files/2008/01/32x_vdp.gif I guess the same thing could also apply to the Genesis VDP (they use the same clock I think) note that it seems some values ...

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Biggest problem is that in order to avoid artifacts you need to turn the display off during HBLANK and the only way to do that and still have enough time to DMA 8 colors is to poll the status register for HBLANK. HINTs occur too late. So you basically end up burning 100% of your CPU time on the col...

No. Why should I do that? It's simple separated TV sync signals. PS I made a device, that generate DTACK, when it not activate in 8 VCLK cycles. You can see it here (add-on in center). One binary counter and simple logic IC. To know the exact cycle count (exprimed in pixel and 68k clocks) for one s...

In the experiments, we get this memory map. Names for signals got from known pictures (Mega01.gif and Mega01.gif). http://img509.imageshack.us/img509/7231/segamapnq0.th.gif Hey excellent work, any chance of probing DTACK activation and number of clk cycles after AS? (speed check) :wink: !DTACK not ...

thank you
I find this very useful

In fact, the question came from disassembling the game "Legend of Galahad" because I noticed a single line glitch on emulator when playing the intro http://gxdev.wordpress.com/files/2007/12/galahad.gif Here, HINT is set to occur at line 176 (and by this I mean AFTER line 175 has been scanned) and th...

Does someone know what happen if display is disabled during line scanning period (clearing VDP register 01 bit 6) ? Is the current displayed line blanked or does this register setting won't apply until next scanline ? Another question would be: for a given H interrupt, occuring after line N renderin...

I think that the issue with soft-reset comes from the fact that, on emulators, "soft reset key" input is handled like any other inputs, i.e at the end (or start) of each frame... so the cpu reset can never occur in a middle of a frame and HV counters are always the same since they are reseted at the...

Charles Mac Donald once said he measured the timer frequency: http://www.smspower.org/forums/viewtopic.php?p=46944 In Genesis Plus, he uses the following formulas: void sound_init(void) { /* Timers run at half the YM2612 input clock */ float clock = ((MCLK / 7) / 2); int i; /* Make Timer A table */ ...

That's right, on a soft reset, the VDP and the main RAM are not reseted ...

I wonder what a real soft-reset precisely do: is it only a simple 68000 reset ? Maybe it also resets the Z80/YM2612 or only the Zbus arbitration logic ?

I have no idea about how to simulate a "rolling screen" so I guess I would leave this unemulated for the moment :wink: ANyway, about the aspect raio: I just realized that the right number of "active" lines (including borders) ouputed by the VDP is 243 lines in NTSC, not 240. (288 in PAL) And that 32...

I can think of 2 games (X-Men 2 & Eternal Champons) that read HV counter to display a random character at power-up

on emulators, since VDP and 68k executions are generally synchronized, this is generally not working properly, the same counter value being always returned at a given CPU cycle

For proper aspect, I'd recommend using a 352x240/288 buffer for H40 modes, and letting the GC scale to 640x480 (you'll see the border, but since the GC does overscan by default that is likely to be hidden). Render your Genesis display to the center 320x224/240 of said buffer (most released games us...

it is very difficult to hear it but the blip sound (it's more something like cymbals, tingtingtingtingting, very fast) is there, in background (which means, very very low) try the same bgm in an emulator (not kega off course) to get an idea about this sound then listen to your OGG again, it's mostly...