Search found 2297 matches

by TmEE co.(TM)
Mon Apr 03, 2017 7:21 am
Forum: Megadrive/Genesis
Topic: Sprite Data Mashed Up
Replies: 3
Views: 701

Re: Sprite Data Mashed Up

Link value isn't being advanced so you only see one sprite.
by TmEE co.(TM)
Sun Apr 02, 2017 7:23 pm
Forum: Sound
Topic: New Documentation: An authoritative reference on the YM2612
Replies: 834
Views: 305979

Re: New Documentation: An authoritative reference on the YM2612

I'd like to add that it is possible to write stuff to YM at sample rate (1 write every 144 YM clocks). I made YM run at same clock as Z80 and made code write one sample every 144 cycles and I got all writes intact. It is not possible to get perfect synchronity to YM like that in normal condition, wh...
by TmEE co.(TM)
Mon Feb 20, 2017 12:11 pm
Forum: Video Display Processor
Topic: Sprite disappearing on certain conditions ???
Replies: 7
Views: 1172

Re: Sprite disappearing on certain conditions ???

I did Y=0 instead of X=0 in my first MD game when I discovered this haha.
by TmEE co.(TM)
Wed Feb 15, 2017 9:39 pm
Forum: Video Display Processor
Topic: Sprite disappearing on certain conditions ???
Replies: 7
Views: 1172

Re: Sprite disappearing on certain conditions ???

EDIT: During rendering, sprite with X coord of 0 can be used to clip sprites with lower priority if it isn't the highest priority sprite on that line. There needs to be at least one higher priority sprite on that line first before clipping can be done, if that condition is satisfied then all lower p...
by TmEE co.(TM)
Wed Feb 15, 2017 3:15 am
Forum: Cartridge
Topic: sram noob?
Replies: 1
Views: 628

Re: sram noob?

There isn't any, you got to do manual address decode. Normally top 2MBytes are used as SRAM range while bottom 2 are ROM range. Games larger than 2MB have a banker that allows top 2MB to be ROM or SRAM depending on last value written to !TIME range. EDIT: Write strobes are !LWR and !UWR, pins B28 an...
by TmEE co.(TM)
Sat Jan 28, 2017 4:01 pm
Forum: Video Display Processor
Topic: Mode 4 VRAM Timing
Replies: 4
Views: 987

Re: Mode 4 VRAM Timing

I snooped around on my SMS2 and it seems to behave same way. In addition blanking has same timings on TMS99xx VDPs on SMS, and possibly same function. TMS does 64 refreshes for DRAMs in blanking during first 256 pixels (and gives 64 access slots) and in remainder of the line there's 42 access slots....
by TmEE co.(TM)
Sat Jan 28, 2017 2:23 am
Forum: Video Display Processor
Topic: Megadrive video timings
Replies: 120
Views: 38335

Re: Megadrive video timings

http://www.tmeeco.eu/Fileden/

Look for same filesnames, I have full backup of all the files I have posted in there. Exactly as my signature here (and everywhere else) says :P
by TmEE co.(TM)
Thu Jan 26, 2017 11:31 pm
Forum: Megadrive/Genesis
Topic: Genesis/MD test ROMs
Replies: 10
Views: 2373

Re: Genesis/MD test ROMs

Look for Nemesis' post in the VDP threads, there's one post with a really big VDP test ROM, there's FIFO in the filename IIRC.
by TmEE co.(TM)
Wed Nov 02, 2016 4:31 pm
Forum: Video Display Processor
Topic: DMA failure on different consoles.
Replies: 12
Views: 1659

Re: DMA failure on different consoles.

ED requires 128KB alignment to work properly, or at least used to require the alignment.
by TmEE co.(TM)
Tue Sep 06, 2016 5:07 pm
Forum: Megadrive/Genesis
Topic: How to build a self-running demo?
Replies: 11
Views: 1733

Re: How to build a self-running demo?

Start your game, record all the input and use that as input for the demo sessions.

EDIT: You can save the keypresse is SRAM and use the SRM file from emulator to get the data to include in your ROM.
by TmEE co.(TM)
Fri Sep 02, 2016 10:34 am
Forum: Announcement
Topic: 10 years!!!
Replies: 7
Views: 1503

Re: 10 years!!!

...wow ! Whole decade ! Häppy birthdéy ~

In december I've been here for a decade also haha
by TmEE co.(TM)
Wed Aug 31, 2016 5:38 am
Forum: Video Display Processor
Topic: VDP access from Z80 questions
Replies: 16
Views: 2388

Re: VDP access from Z80 questions

During fills the CPU runs yeah, but not during other DMAs. 68K will be halted and so will be Z80 if it tries to access 68K side during a DMA.

See page 15 here : http://www.tmeeco.eu/SMD/Genesis%20Soft ... -09%5D.pdf
by TmEE co.(TM)
Tue Aug 30, 2016 3:40 pm
Forum: Video Display Processor
Topic: VDP access from Z80 questions
Replies: 16
Views: 2388

Re: VDP access from Z80 questions

When DMA is in progress the CPU is halted, no ints will happen or anything else. And there's only one case where VBL and HBL ints can happen at the same time which is the very last active display line.
by TmEE co.(TM)
Thu Aug 25, 2016 6:35 pm
Forum: Sound
Topic: Set volume of both sound chips
Replies: 3
Views: 973

Re: Set volume of both sound chips

There's no master volume anywhere, so you got to play with the volume registers on PSG and TL register on YM.
For YM you have to keep track of current algorithm and adjust TL equally on all output operators. One step is 0.75db on YM and 2db on PSG.
by TmEE co.(TM)
Sun Aug 21, 2016 3:08 pm
Forum: Video Display Processor
Topic: VDP access from Z80 questions
Replies: 16
Views: 2388

Re: VDP access from Z80 questions

Z80 cannot do 16bit accesses to the VDP, the 8bit accesses done by Z80 (or 68K) to VDP are always seen as 16bit accesses (both halves of the 16bit write will be duplicated). You can get more info from the docs by Charles MacDonald.