But frequency of H-Interrupt and V-Interrupt are more important too?
I always thought these interrupts depended of the position of the TV electron beam?
Search found 256 matches
- Sat Mar 07, 2009 5:50 pm
- Forum: Video Display Processor
- Topic: HBlank Timings
- Replies: 163
- Views: 99170
- Sat Mar 07, 2009 12:28 pm
- Forum: Video Display Processor
- Topic: Megadrive video timings
- Replies: 123
- Views: 163071
- Sat Mar 07, 2009 12:25 pm
- Forum: Video Display Processor
- Topic: HBlank Timings
- Replies: 163
- Views: 99170
Thank you Eke for all this information. I understant now more precisely how the vdp work :-) I expect Jorge will make same measure for PAL Timings :-) If you overclock the vdp, the pixel clock is overclocked too, so the pixels are generated more quickly, so the frame displayed on the screen is wrong?
- Sat Mar 07, 2009 11:48 am
- Forum: Video Display Processor
- Topic: Megadrive video timings
- Replies: 123
- Views: 163071
- Fri Mar 06, 2009 11:28 pm
- Forum: Video Display Processor
- Topic: HBlank Timings
- Replies: 163
- Views: 99170
Yes i made error with my calculs. I calculated Number of Master Cycles correctly but not converted in good number of H32 pixels, so i correct them in my post. Hblank period is composed by end of HSync + start of front porch + end of front porch + front border, wich correspond to 147 MCLks? So the 7 ...
- Fri Mar 06, 2009 8:51 pm
- Forum: Video Display Processor
- Topic: HBlank Timings
- Replies: 163
- Views: 99170
isn't it 147 EDCLK acoording to your values? And : 87*4 + (147 - 87) * 5 = 648 MCLKS? So in theroy for H32 mode : 8 (back border) + 18 (back porch) + 7 (start of Hsync) = 53 EDCLK = 26 "H40 pixels" = 212 MCLKS = 42,4 "H32 pixels" (Corrected after Eke post : 212/10 = 21,2"H32 pixels") 57 (end of Hsyn...
- Fri Mar 06, 2009 6:15 pm
- Forum: Video Display Processor
- Topic: HBlank Timings
- Replies: 163
- Views: 99170
So according to Charles MCDonald, HBlank period is 10 pixels in H40 mode wider than in H32 mode (E9 - E4 = 5; 5 * 2 = 10 pixels) ? So 69 or 70 pixels = approx 552 MClks in H40 mode (69 * 8 = 552) ? Another question : In Jorge timing post, when you calculate timings, you said that in H40 mode there a...
- Fri Mar 06, 2009 2:54 pm
- Forum: Video Display Processor
- Topic: HBlank Timings
- Replies: 163
- Views: 99170
- Mon Mar 02, 2009 8:37 am
- Forum: Video Display Processor
- Topic: HBlank Timings
- Replies: 163
- Views: 99170
The problem i have with sonic 2 is due to the timings i use : H-INT : 0 HBlankStart = H-INT + 130 MClks HBlankEnd = H-INT + 130 MClks + 860 Mclks So the delay between H-INT and HBlankEnd is 990 MClks The 68K needs 44 Clks (308 Mclks) to fetch registers before executing first instruction of the inter...
- Fri Feb 27, 2009 7:20 am
- Forum: Video Display Processor
- Topic: HBlank Timings
- Replies: 163
- Views: 99170
- Thu Feb 26, 2009 7:18 pm
- Forum: Video Display Processor
- Topic: HBlank Timings
- Replies: 163
- Views: 99170
- Mon Feb 16, 2009 12:16 pm
- Forum: Video Display Processor
- Topic: Megadrive video timings
- Replies: 123
- Views: 163071
- Mon Feb 16, 2009 8:51 am
- Forum: Video Display Processor
- Topic: HBlank Timings
- Replies: 163
- Views: 99170
This week end i made tests with this timings. All games seems to work correctly. To resume : - Line rendering at HBLANKSTART + 36 cycles 68k - Correct c68k core. Now 68k return 44 cycles before executing first instruction. So the first instruction of interrupt process is executed at HBLANKSTART + 44...
- Mon Feb 16, 2009 8:51 am
- Forum: Video Display Processor
- Topic: HBlank Timings
- Replies: 163
- Views: 99170
This week end i made tests with this timings. All games seems to work correctly. To resume : - Line rendering at HBLANKSTART + 36 cycles 68k - Correct c68k core. Now 68k return 44 cycles before executing first instruction. So the first instruction of interrupt process is executed at HBLANKSTART + 44...
- Fri Feb 13, 2009 4:37 pm
- Forum: Video Display Processor
- Topic: HBlank Timings
- Replies: 163
- Views: 99170