Search found 463 matches

by ob1
Mon Feb 05, 2007 9:50 pm
Forum: Super 32X
Topic: GLide 32x
Replies: 38
Views: 37363

GLide 32x

Although I have real difficulties seeing my code running on the 32X (debugger, anyone ?), I have a silly idea in the head : a rendering library, let's call it GLide, for the 32X. link : http://www.alasir.com/software/glide/index.html The 68k would put data on the Comm Port, and each SH2 would poll i...
by ob1
Mon Feb 05, 2007 1:43 pm
Forum: Super 32X
Topic: Any way to run 32X VDP without hurting MD mapping?
Replies: 7
Views: 10072

The Hardware Manual states that, once it (ADEN bit) has been set, further "change (is) not allowed".
by ob1
Mon Feb 05, 2007 9:50 am
Forum: Super 32X
Topic: Frame Buffer Switch
Replies: 5
Views: 7259

I thought they were quite the same. Can't I do the same things ? Let's suppose I want to draw a 165 pixels long red line, from pixel 48, the others being black. With RLE : 2F00h, A401h, 6A00h with palette : 00h : 0000h black 02h : 7C00h red With FILL : 002Fh, 2000h, 0000h 00A4h, start address is alr...
by ob1
Mon Feb 05, 2007 9:22 am
Forum: Super 32X
Topic: Frame Buffer Switch
Replies: 5
Views: 7259

I was wondering what that FILL function was for ! I didn't see the use since the Run-Length is fine for continous pixels (if less than 255). FILL for clear, why not. The doc states the FILL execution time is 7+3xlength, and the SH2 to DRAM execution time is 1-3 cycles. Is the FILL faster than direct...
by ob1
Mon Feb 05, 2007 9:04 am
Forum: Super 32X
Topic: Frame Buffer Switch
Replies: 5
Views: 7259

Frame Buffer Switch

Just a little question. The 32X has 2 frame buffer : FB0 and FB1. When FB0 is displayed, I can write to FB1. Calling the frame buffer swap, FB1 is displayed and I can write to FB0. But is this frame buffer emptied or does it still have previous data ? eg : FS = 0 I draw a red triangle. FS = 1 I draw...
by ob1
Sun Feb 04, 2007 7:56 pm
Forum: Super 32X
Topic: FIFO
Replies: 10
Views: 10977

FIFO

Hi you all. Still on 32x dev' ;) I'm looking at the FIFO. First of all, is it usable ? Or is it DREQ only ? The 68k writes to A1 5112h, and the SH2s read 2000 4012h. But is it a stack, a heap or anything ? And if so, how big is it ? I mean, if the 68k want to put several datas, does it have to wait ...
by ob1
Wed Jan 31, 2007 10:33 am
Forum: Super 32X
Topic: Cache coherency
Replies: 8
Views: 9870

For sure ! And by the way, use private RAM if the data is less than 2KB . Enable 2-way cache (and thus, 2KB of private RAM) : mov CCR,r0 mov #$19,r1 mov r1,@r0 ; Enable Cache, set 2-way, and purge CCR: dc.l $FFFFFE92 Then, private RAM is from C000 0000h to C000 07FFh. I don't know how fast the cache...
by ob1
Wed Jan 31, 2007 7:48 am
Forum: Super 32X
Topic: Cache coherency
Replies: 8
Views: 9870

Cache coherency

As said before (mask of destiny), the SH2 doesn't have any mechanism for cache coherency. When a CPU writes to memory, the other CPU has no mean of knowing the data he might have in its cache has to be invalidated. I've thought about a mechanism : each time a CPU write to memory, it puts the address...
by ob1
Sat Jan 27, 2007 9:56 am
Forum: Super 32X
Topic: Master SH2 BIOS
Replies: 12
Views: 18309

Stef wrote:... you have to use the cache and register as much you can.
Got it !

But man, ... I've never thought of developping software tile distortion .... I miss the Saturn VDP 1 (sigh...)

Anyway, coding a fill polygon function is quite of a challenge, and stimulating enough !!!
by ob1
Fri Jan 26, 2007 11:31 pm
Forum: Super 32X
Topic: Master SH2 BIOS
Replies: 12
Views: 18309

I've been thinking of what you told me for an hour, and I conclude that you're absolutely right : any mean that makes memory access or rate go faster will be welcome !

Great piece of advice, Fonz'
by ob1
Fri Jan 26, 2007 11:02 pm
Forum: Super 32X
Topic: Master SH2 BIOS
Replies: 12
Views: 18309

the main problem with 32x is the DRAM / VRAM speed... Are you sure the SDRAM speed, or FB speed is the main problem ? I would have guessed some missings features were much more a concern : no fill polygon, no scroll no scaling/rotation/distortion ... no hardware graphics function. Anyway, there are...
by ob1
Fri Jan 26, 2007 5:49 pm
Forum: Super 32X
Topic: Master SH2 BIOS
Replies: 12
Views: 18309

Not change, but set. The 7604 Hardware Manual states in £7.5.8 (Power-On Sequence) that CAS latency must be set before any CS0 access. So you've got to write something (any data) to register : - FFFF 8426h for CAS latency 1, 16 bits - FFFF 8446h for CAS latency 2, 16 bits - FFFF 8466h for CAS latenc...
by ob1
Fri Jan 26, 2007 3:58 pm
Forum: Super 32X
Topic: Master SH2 BIOS
Replies: 12
Views: 18309

Master SH2 BIOS

Here's a disassembly of the Master SH2 BIOS : org $0 * VBR dc.l reset ; 0: POWER ON RESET PC dc.l 0x06040000 ; 1: POWER ON RESER SP dc.l reset ; 2: MANUAL RESET PC dc.l 0x06040000 ; 3: MANUAL RESET SP dc.l forever ; 4: GENERAL ILLEGAL INSTRUCTION dc.l 0x00000000 ; 5: SEGA RESERVED dc.l forever ; 6: ...
by ob1
Fri Jan 26, 2007 3:54 pm
Forum: Super 32X
Topic: 32x "security code" reverse engineered
Replies: 27
Views: 47085

Did you manage to run both SH code actualy? Not today ! My boss won't be happy since I've done ... nothing this week !!! Once more !!! But, I've understood everything I wanted ! I get the boot process ! Next step will be to write something in Frame Buffer from just one SH2. Next step will be to plo...
by ob1
Fri Jan 26, 2007 3:47 pm
Forum: Super 32X
Topic: 32x "security code" reverse engineered
Replies: 27
Views: 47085

I've found out that the Master SH2 bios checks the initial program of the cartridge. So, it has to be present in rom, and it is present !!! From $36C to $76C !!!