SpritesMind.Net

Very interesting. Let me comment: The thing is that, if your implementation is correct, it would take a maximum of 18+23=41 cycles to update the keyon states of all four operators. Which means, you could write a certain keyon value, wait the 32 cycles the dumb BUSY timer (and the datasheet) told you...

I am glad to see the thread still alive. We do not know everything about the YM2612 yet ! About this one, I've run a few tests on VA4 MD1 (with discrete YM2612) and VA0 MD2 (with 315-5660 ASIC) regarding the BUSY flag and here is what I figured or confirmed from Sauraen die shot analysis : 1) BUSY f...

Sauraen wrote:The only sort of protection I've seen on the chip is some sort of resistor on the digital input pins. The YM2612 isn't CMOS so large protection transistors (really diodes) weren't required.

I see. ESD really became popular with CMOS processes.

Hi all, I have finished reading the full thread and I have enjoyed every bit of it. Let me add to it now. First , I am working on a verilog module that replicates in hardware the YM2612/YM3438 to a very precise level. The internal operation is likely to be pretty much the same as the original. Every...

Problem is that you can't read anything from YM2612 except status. Sauren have found debug stuff, but I doubt it's usable from MD. The operator data output mode should work from MD too... except there is no way to output the data to a memory... :| Indeed I just need to check some minor things that ...

Your methods look correct but if you use SGDK, why are you rewriting all these methods which already exists ? Z80_requestBus(..) Z80_releaseBus() YM_writeRegSafe(..) YM2612_writeRegSafe(..) I think there is everything you need to do some basic YM tests. Thank you! I used these functions and was abl...

Hello, This is my first post. I am developing a Verilog version of YM2612, which will be used to run the Genesis on FPGA. I have been doing it with the help of Sauraen, who is a member of the forum. I am quite advanced with this and now I can actually run the Genesis on FPGA. I have some issues with...