Search found 81 matches
- Mon Dec 07, 2009 12:36 pm
- Forum: Megadrive/Genesis
- Topic: Neo Myth Menu beta
- Replies: 36
- Views: 21343
Hi Chilly, It's tough to be certain without being able to play around with the code. I think I may know where some of your performance is going. The filesystem code calls disk_readp repeatedly when doing things like getting directory lists. The sector is always the same between calls, but you always...
- Sat Oct 31, 2009 5:06 pm
- Forum: Blabla
- Topic: More 315-5313 unknown stuff (speculation)
- Replies: 52
- Views: 45711
- Mon Sep 14, 2009 11:32 am
- Forum: Super 32X
- Topic: 32X BIOS on MD side
- Replies: 6
- Views: 7157
Really? By writing some 8 values to $A130F1? That's not what this code does: ROM:000000E8 loc_E8: ; CODE XREF: ROM:000000EEj ROM:000000E8 move.b (a0)+,(a1) ROM:000000EA adda.w #2,a1 ROM:000000EE dbf d7,loc_E8 It writes 8 values to 8 addresses, each two bytes apart - $A130F1, $A130F13, $A130F5, etc....
- Wed Aug 26, 2009 11:29 am
- Forum: Megadrive/Genesis
- Topic: newbie's questions
- Replies: 35
- Views: 21635
That's really strange.
Should be exactly the same as
The same is true of operator |. Are you sure something else wasn't out of place?
Code: Select all
VDP_setTile(APLAN, 1<<13^130, 3, 10);
Code: Select all
VDP_setTile(APLAN, 130+(1<<13), 3, 10);
- Sat Aug 15, 2009 6:04 pm
- Forum: Demos
- Topic: SEGA GENESIS VGM PLAYER
- Replies: 48
- Views: 53493
- Tue Aug 11, 2009 12:18 am
- Forum: Super 32X
- Topic: DMA to PWM
- Replies: 43
- Views: 47884
I applied my new found knowledge to the problem and now have perfect playback - sounds great. Just to recap, in case anyone like me stumbles across this years from now... Set Cycle Register (0x20004034 on SH2) to base clock / sample rate Send unsigned PCM data scaled to 1 to (Cycle Register - 1) to ...
- Mon Aug 10, 2009 12:46 am
- Forum: Super 32X
- Topic: DMA to PWM
- Replies: 43
- Views: 47884
- Sun Aug 09, 2009 8:34 pm
- Forum: Super 32X
- Topic: DMA to PWM
- Replies: 43
- Views: 47884
- Sun Aug 02, 2009 6:22 pm
- Forum: Super 32X
- Topic: DMA to PWM
- Replies: 43
- Views: 47884
PWM DMA works... on the slave, not the master. Argh! I've only been using the master! Still haven't had any success, but I don't have time to check anything else right now. I'll move to the slave when I get a chance in a week or so. BTW, does anyone have the utility that converts AIFF to PWM sample...
- Sat Aug 01, 2009 3:09 pm
- Forum: Super 32X
- Topic: DMA to PWM
- Replies: 43
- Views: 47884
I've been testing on emulators so far. I had been using GensKMod until I realized that it didn't support DMA. I've also tried Gens/GS and Kega. I guess I'll stick to real hardware from now on. PWM sound seems to work in every game I've tried on Gens, so I guess not too many use DMA. Does anyone know...
- Fri Jul 31, 2009 11:56 am
- Forum: Super 32X
- Topic: DMA to PWM
- Replies: 43
- Views: 47884
- Fri Jul 31, 2009 12:25 am
- Forum: Super 32X
- Topic: DMA to PWM
- Replies: 43
- Views: 47884
DMA to PWM
I'm trying to get DMA to the PWM controller working and am having no success. Here is what I am doing: SAR1 = source address (in ROM, SH2 address space) DAR1 = mono pulse width register (0x20004038) TCR1 = 1024 (some number long enough that I'd notice the output) CHCHR1 = 0x14E1 (fits Sega's 00XX 01...
- Tue Jul 21, 2009 11:49 am
- Forum: Super 32X
- Topic: Shared Memory
- Replies: 16
- Views: 12916
Right, I see. I did some more reading and some experimenting and I think I get it now. Here's how I understand things: 68K communicates destination address and length to SH2 somehow (maybe through communication registers or though the 68K DMA dest registers). SH2 writes destination address and lengt...
- Mon Jul 20, 2009 11:01 pm
- Forum: Super 32X
- Topic: Shared Memory
- Replies: 16
- Views: 12916
- Mon Jul 20, 2009 11:45 am
- Forum: Super 32X
- Topic: Shared Memory
- Replies: 16
- Views: 12916
Actually, I was planning to put commands and data into a buffer in memory and then write the offset of that buffer into the comm port. This triggers an interrupt which causes the SH2 to act on that data and update it's read pointer (another comm port register). 16 bits per transfer isn't enough. I g...