SpritesMind.Net

As you can see I tried loading the vector table to the best of my knowledge to address 0xFFFD00, which is supposedly the area it should be loaded to. This of course was just an assumption and my n00bish attempt at doing so. I have dumped the RAM with Gens without doing it and doing it, and if I don...

Stack won't work at an odd address.

Try this instead:

The fig 3-3 at page 7 of mega cd disk format doc isn't clear about Main CPU & Sub CPU part. That figure isn't clear about anything. :lol: Ok...I found the encoded CD Bios, default SP and PCM I also find the uncompress method (need to understand it).... Note: they are encoded in the LZSS-variant com...

I was using the decompressed Sega CD 68k BIOS from Eidolon which must be the CD Bios without the jump table... The "decompressed" file at Eidolon's is a bit misleading. It is actually a memory snapshot after all parts of the bios have been loaded to subcpu prg-ram. It is a combination of 3 decompre...

I thought the first 1M was the BIOS rom so a call to 5F22 mean a call the BIOS's 5F22.... but there is nothing (usefull) at 5F22.... So, it seems I'm missing how the BIOS is loaded/used..... The subcpu bios occupies 000000 thru 0057FF and uses ram space at 005800 thru 005FFF for stack and variables...

Not fusion. Gens (different builds of it). Is it the same GST format for Fusion? Not quite. For Gens Tracer (and probably others): 0x25550: SUBCPU REGS 0x25950: GATE ARRAY (COMM...) 0x26550: PRG-RAM (BYTESWAPPED) 0xA6550: WORDRAM (BYTESWAPPED) 0xE6550: PCM-RAM The byteswap is a bit of a nuisance, b...

If the CD audio tracks are not loaded, it won't work. Shouldn't be any problem if all the files are named correctly, though. Anyway, I was looking at the save state file and it has the GST tag at the beginning. Anyone have information for the CD part of this format? For Fusion? I have this: 0x22478:...

A minor gripe: The manual says the maximum wait time for VRAM writes (to a full FIFO) is 4.77us in H40 mode. Let's see: SC in H40 mode is MCLK/4, outside of H-sync. Because of the refresh cycle, there's a gap of 16 access slots between external access slots. So, that's a maximum wait time of 4/MCLK ...

Thanks to Nemesis's discoveries about VRAM access ( that post ), the effect is pretty much explained. To change a whole palette (16 word entries) on one line, the display is disabled, the palette data is DMA'd to CRAM, then the display is reenabled. Obviously this is done during the H-blank period a...

Awesome, Nemesis! Can't wait for more.

Some games, like this one, are quite friendly, allowing you to simply provide a filename and have that file loaded where you want it. Some games will index their files in a separate table, bypassing the ISO directory entirely, so that files are referred to by number, not name. It varies. You can pro...

Note, if you want to do a proper soft reset, you'll need to reset the stack pointer.

This should work:

Anyway, I'm good on BIOS calls, but what would a jsr to $7880 or $7800 do. I can't seem to find that anywhere in these documents but I see it several times in the (either IP or SP code, still figuring that one out). SP (subcpu boot code) loads to $6000, so it's probably right there. $7800 @ loc_280...

The PCM address registers each have an 11-bit fractional component (2^11 = 2048). Technically, the sampling rate is fixed at 32KHz, and FD serves as an increment to the address register. In a sense, you could say that a PCM RAM pointer is advanced by FD/2048 bytes at every clock (32KHz). So, if FD =...

I have it as: Sample rate = FD * PCM clock / 2048, where PCM clock = 12.5 MHz / 384 = 32552 Hz approx.

SR = (FDH * 256 + FDL) * 12500000 / (384 * 2048)