SpritesMind.Net

According to Charles McDonald, CD4 does nothing in non-DMA mode. A register write changes the mode to VRAM read if I understood this correctly, but the effect on the current address is unknown. Another thing to try is setting CD4 to 0 with VRAM copy mode selected in register 23, or setting it to 1 w...

My guesses: xx0111: write same value to CRAM and VSRAM? xx1011: short circuit or AND/OR to CRAM? xx1100: short circuit or read AND/OR between CRAM and VSRAM? 110100: duplicate high bytes from VSRAM to VRAM or copy high bytes within VSRAM, setting low bytes to unknown value? 111000: duplicate high by...

It's so that you don't have to actively wait for the line counter to reach a specific value, but can do other things in the meantime. H interrupts let you know when a specific number of lines have passed, so that you can change something. For example, in Sonic, the H interrupt handler changes the pa...

Yes, by a command I just mean something which specifies a large object to be made out of 16x16 blocks, just like in those Nintendo titles. If you load the level data into RAM as tiles first, transferring them will take just a short time because you don't have to interpret the level data as you draw....

Changing GCC version or using different options can not fix this error, since it has nothing to do with GCC. The error is in sega.s, which is part of the library. It can show up if your program exceeds a certain size. The errors are on line 152 and 159, which read: bsr _hblankcallback bsr _vblankcal...

Remember to have a move.w #$2300,sr somewhere in your setup code. And to get H interrupts working, you have to set up the line counter initial value (VDP register 10). If you only use it once per frame, you can disable the H interrupt when it's reached. If you use it multiple times in one frame, it'...

In Mega Man 5, the GG code ATLKGL (C33C:60) enables debug keys on controller 2. Some of these are processed in the main game task (Task 0). These are Left (pauses the game) and Right (palette editor). Task 1 handles palette and background animations. Task 2 just starts up the other tasks. Task 3 is ...

Nope, not PC, Mega Drive. I used the same technique on the NES. I switch to loading task at the end of frame processing, and the VBL handler returns me back to where I was before. Many Capcom NES and SNES games have support for (non-preemptive) multitasking too in the code, although they don't usual...

For tile updates, you could transfer a manageable number of tiles every frame until you're done. Uncompressing can be done in the background when the game is idle. In an upcoming game I'm making, I switch to a background task that performs loading of world data whenever I'm waiting for the next fram...

Is the CPU frozen during DMA even if it's running from RAM? Because Sega recommends triggering the DMA copy with the source operand in RAM if the copy is from ROM to avoid a hang.

No, that's not true. The wait states would happen around 255714 times per second, which is a frequency much higher than what we can hear.

Yes, using wait states would be a good idea.

All games I've disassembled use cycle counting to time DAC playback. I haven't heard of any games that use timers for anything but music timing.

Digitized sounds would be off key. Usually, they're only used for drums, but Phantasy Star 4 has some melodic samples in it, and the music would not sound right.

If you can use a normal signal as a clock input, it shouldn't be hard to use the top bit of a counter counting to 15 as a clock signal.

Sorry, my mistake. It should work now. Try downloading and testing it again.

Well, Phantasy Star 4 uses a special I/O port to switch between SRAM and ROM, so that's probably unimplemented.