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68K duplicates high and lwo bytes during 8bit writes (i.e $12 is $1212 on the bus). Reads are aways 16bit and CPU internally chooses which half to use depending on address. That make sens. From design code point of view this behavior have to be in my 68K core code, not in my vdp code. if (addr & 1)...

68K duplicates high and lwo bytes during 8bit writes (i.e $12 is $1212 on the bus). Reads are aways 16bit and CPU internally chooses which half to use depending on address. That make sens. From design code point of view this behavior have to be in my 68K core code, not in my vdp code. if (addr & 1)...

From Genesis Plus GX Source : void vdp_write_byte(unsigned int address, unsigned int data) { switch (address & 0xFC) { case 0x00: /* Data port */ { vdp_68k_data_w(data << 8 | data); return; } case 0x04: /* Control port */ { vdp_68k_ctrl_w(data << 8 | data); return; } case 0x10: /* PSG */ case 0x14: ...

I'm talking about the cpu register. When you do read access with upper byte the cpu take the upper byte (D15-D8) from the bus and put this byte into lower byte of register. Now, at the contrary, what happen if you do write access to vdp control port with - UDS selected (<=> write byte at even adress...

From my point of view when uds is selected the 68k put the upper byte of data bus into lower byte of register.

Is this the way i emulate my vdp access : u32 Vdp::readWord(u32 adress, u32 ctrl) The method return D15-D0 lines (Word) U32 adress : A24-A1 lines adress (A0 is bit 0 but is ignored) u32 ctrl : Bit 0 : LDS, Bit 1 : UDS Let's take an example of reading upper byte from Control data port from the 68K si...

I have a question about the vdp/68K connection. The VDP is connected to UDS/LDS signal from the 68K. What the consequence for the vdp internally, for example, of reading upper byte (UDS = 0, LDS = 1) of Control/Data or HVC Counter? Does the VDP return only upper byte on the D15-D8 data line and does...

When you assert bus request, what you're doing is asking the Z80 to let its bus alone — which may take a bit of time, since it needs to finish any ongoing access first. You're supposed to read back from $A11100 to know when the Z80 has done that. The problem is that while the Z80 is reset it will n...

It's… messier than that: https://plutiedev.com/using-the-z80#loading-z80 Or also from the Sega docs (though it's essentially describing the same thing): Z80 Start-Up Z-80 Operation Sequence: BUS REQ ON BUS RESET OFF 68k copies program into Z-80 S-RAM BUS RESET ON BUS REQ OFF BUS RESET OFF The bigge...

Thank you!

I'm using this thread to ask a question about Reset et BusAck signals from the Z80.
While the Z80 is resetting (RESET Pin in low state) how is the BusAck Signal?
If the BusAck Signal is low that mean the 68k can read/write the Z80 bus (That what i understand from this post).

Another question : what happen if the Z80 request the M68000?
The M68000 stop to execute opcode or it continues until it have to do a memory access (and at this moment it wait that the busreq line be back to 1)?

That confirm what i had in my mind ...
Thanks Sik !

I have a question about the control and data ports of the genesis.
Are these ports inside the vdp chips?
Often in emulator code these ports are outside the vdp code file.

Impressive work nemesis i will read all your documentation with much interest !