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and I use .ASM or .S to go through my macro preprocessor to generate .s

From what I know, I'm not aware of a standard.
Some of them are inherited from old 68K asm editor.

The only reason I use different extension to be sure the right assembler will be called on my makefile

SCOR period: 1/75 sec. which prove MCD is 1x CD drive and you do understand why I wanted to check fi SCOR was in sync with IRQ which 1/75sec too Yes, but nIRQ is not 1/75. It is most like 1/150. 1/75 is what's on MCD 1 manual so it's strange.....(it's written 1 frame = 1/75s) http://savepic.ru/1464...

It is quite logical. When reader detect S1 (while S0 already in internal buffer/register) it set SCOR for one subcode byte. And reset it on first non Sx subcode. It is not necessary to set it for 2. http://savepic.ru/14666828.png To be honest, i know the answer was on this picture...but I was unabl...

HardWareMan wrote:SCOR period: 1/75 sec.

which prove MCD is 1x CD drive

and you do understand why I wanted to check fi SCOR was in sync with IRQ which 1/75sec too

THANKS !!! awesome !!! so, for me, the only question still here (for now) is why SCOR is only 1 frame and not 2 like it should be : A sector is 98 frames, with 2 frames for S0/S1 synchronisation word and 96 frames for subcode = 96bit for P, 96bit for Q,...... so where is the second frame ?! oh, and ...

I forgot control channel. Here is power up OHHH !!! IRQ is not sent EVERY 1/75s ?!!! Does it mean the next IRQ is sent only when command received is proceeded ? to be able to sent result on next IRQ ? it would answer my question about sync how comm / sub / data I would then mean IRQ status = xxx co...

OK. I think we can do first approach to make FLASH player of CD image. The only thing is still undiscovered is set of commands and statuses on control 4 bit bus. I think it's not that hard... difficult for someone like me who'll need to learn VHDL & FPGA at the same time (in progress...very interes...

Same here (no audio disk -> audio disk load -> audio disc play) so subchannel data is sent even when SCOR occurs, thanks ! What I can't explain is why SCORE is ONE WFCK only and not TWO (S0 & S1) i don't understand... You can use my captured data to decode playing time and other control data. Just ...

I've got it. The CD track is kind of tape with 74/80/99 minutes of play, digitally. So, when it carries an audio data, there no need a perfect sync, so rough time coordinate is M:S:F format in subchannel. When they turn the audio CD to the data CD, there must be more accurate sync to the "tape". So...

Did you saw this diagrams before (they come from Mega CD 1 manual)? Sure it was my first source of info ;) and the Mega CD2 manual got some more It seems that 48 bits in transaction, 24 bit for every channel and it is use 16 bit with right align and sign extend (D16...D23 is copy of D15). yes, 16bi...

It's exactly because of the 6B joypad that I asked this.

From what i know, won't work

I remember a talk about how fast the reading should be to avoid "reset" for 6B pad, multiplayer,, .....

It became very difficult if I have

MD_5V <=>level shifter <=>FPGA 3.3V<=>level shifter <=>DEVICE_5V ;(

I read something about a Cypress PSoC 5V which include a µC and some king of FPGA...need to find it and get more details

Controller data is read by switching TL/TH
You have to switch them an even times.

What would happen if, by mistake, I switch them an odd times?
has the controller somekind of reset-to-defaut-after-X-ns feature ? or will my read be bugged for the rest of the game ?

If you can log every pin, you'll make my day !!
yes, I'm, for now, interesting by the flow on this FFC.

i was planning to remove the faceplate to get access to the pins while power on, not easier ?

Making the log request below ( ), I suddenly realize the sync words are 14 bits
I don't know how they will be converted to 8 bits (14 bits EFM -> 8 bits data)