SpritesMind.Net

I think it's just you are not talking about the exact same thing. EDCLK pattern is definitively 15 pulses at MCLK/5 followed by 2 pulses at MCLK/4, this can still be seen in Tiido pictures, even the second one where he observed pixels with 9 MCLK cycles . Pixel clock (SCLK) pattern is different beca...

VA0 has neither a 315-5339 nor a 315-5345, but instead has an EDCLK generator made out of 74-series logic on a daughter board . There's also at least one 74-series chip on the main PCB between the work RAM chips (presumably for the A14/OE fixes for SMS/MarkIII mode). I know yes, what I meant is tha...

SCBR is generated by the VDP so it's probably an input. Interestingly, this signal isn't connected to the 5364 chip in the VA3 at all. It just goes straight from the VDP to the color encoder. Actually, are you sure this is actually SBCR (connected to VDP pin 50) and not VCLK (connected to VDP pin 4...

The new tilemap data snaps in entirely during one frame, as if the fifo was massive, but I can't think of any reason for the delay. That is most likely the case, the clone is probably using a much larger FIFO (or a VRAM cache). Remember that: 1) DMA will release 68k bus and software execution as so...

Some more news about YM2612 DAC "ladder" effect: a guy named Nuked who analyzed YM3438 die shots recently wrote a cycle-accurate implementation in C and figured the effect was actually caused by two things: 1 ) the fact that the resistor array would not exactly reach Vcc/2 on either negative or posi...

Yes, it was mostly emulated by reversing the various games that use it and then later completed (the unused buttons mostly) using some XE-1AP driver code that was posted on sega-16 http://www.sega-16.com/forum/showthread.php?30101-XE-1AP-Analogue-Controller-Cyber-Stick-CZ-8NJ2-XE-1AJ-Driver-%28Sourc...

Small update to flamewing's test to trigger a bug in Genesis-Plus-GX at least: https://github.com/flamewing/68k-bcd-verifier/pull/1/commits/8e917e6a6dffe4724c6432c10efde0e3afd720bf http://notaz.gp2x.de/md/rel/bcd-verifier-u1.zip Well, this was indeed a very stupid bug in Musashi: upper bits of NBCD...

I don't know if those are already known but I found these manuals recently https://console5.com/wiki/File:JVC_X%27Eye_RG-M10BU_Service_Manual,_No._20478,_April_1994.pdf https://console5.com/wiki/File:JVC_Technical_Manual_X%27Eye_RG-M10BU,_1994.pdf They are quite interesting to read compared to other...

That's not it, no. Let's ignore Ballz 3D and presume a test ROM: We set up for a VDP DMA fill operation and set CD5, but then we don't write the fill byte. And there's no FIFO slots available to pull it from, the FIFO is totally empty. Instead, we poll the VDP status bit 1 (DMA) waiting for it to b...

What I think you are missing, as far as I can tell: - for vscroll, value read from VSRAM must be shifted right by one (VSRAM width is 11-bit but bit0 is ignored in interlaced mode 2) before being added to vcounter value (9-bit) - for sprites, when preparing the sprites list (i.e looking which sprit...

What I think you are missing, as far as I can tell: - for vscroll, value read from VSRAM must be shifted right by one (VSRAM width is 11-bit but bit0 is ignored in interlaced mode 2) before being added to vcounter value (9-bit) - for sprites, when preparing the sprites list (i.e looking which sprite...

Yes, that's pretty much it

The 'issue' is that VRAM byte writes (used by VRAM fill and copy DMA) actually occur to VRAM address ^ 1 so you can get unexpected results depending on start address, DMA length and increment alignments. In your case, when VRAM address reaches F000H, last write occurs at F001H instead of F000H. I th...

I can't really tell what you're doing from the values, but 3-line handshake is simple: start with unselected (0x60), then toggle back and forth between the two selected states (0x20 and 0x00) to get nibbles (0x20 first). That's all there is to it. When you're done, deselect the mouse again (0x60). ...

I'm guessing the oo means it timed out? Yes. It seems to indicate the mouse does not respond to handshake request when TH is low unless it was properly reseted (60h followed by 20h or possibly 00h). If you don't mind, I added a few write sequences for completeness in this test ROM. This should be t...