SpritesMind.Net

Yeah it's really just using different table values. You only need to change a couple values to make it behave exactly like the arcade version in that respect. I guess it's a little awkward either way because of the loop around.

Anyway, good luck on your high score attempts! Flicky is quite a ...

Hey matt,

Here's the deal. The window bonus is given based on performance over every 8-round span, starting with round 3. If you earned it, it comes in the last of those 8 rounds.

To get the bonus, you need to (for each stage):
- deliver all the chirps at once
- finish within the time limit (see ...

The parameterization PLA has a 32-bit bus but the article seems clear that it is a 16-bit bus containing the operation word (IR register) and the other 16 bits are the complement of those. So maybe this isn't the 32-bit bus the address bus drives?
You seem to be confusing the parametrization PLA ...

I have some idea how to handle this properly but I have difficulties understanding what hardware is really doing: why setting source address one word above would fix VDP slow read-out ? Does it mean the first word read is not read properly and instead written to the next VRAM address ? What about ...

That's what I was doing before but it appeared it broke Willy Beamish Logo: see how it only rewrites reg 22 (and reg 23) but expects LSB to be reloaded with reg21 as well. If I leave reg21 to the final value it reached after previous DMA, I got those graphic errors.
I see what it's doing. But if ...

In assembly, 'if a <> b then blah' becomes 'if NOT a <> b then branch'. So, in your case:

* if e2 > -dy then blah
becomes
* if e2 <= -dy then branch

That BGT (Branch if Greater Than) should be BGE (Branch if Greater or Equal).

* if e2 < dx then blah
becomes
* if e2 >= dx then branch

That BLT ...

So I attempted to port this: http://en.wikipedia.org/wiki/Bresenham%27s_line_algorithm#Simplification
over to the genesis but for some reason it does not work correctly I have looked at each line of code at least 10 times each if not more and I can not understand what the problem is.
In general ...

What I don't understand is what triggers those CDC host reads. I guess it's initially coming from a ROMREADxxx command sent to the BIOS but I can't seem to find what make the BIOS initialize CDC (CDCSTART command ?), enable buffer RAM writes for a few sectors then suddenly stop it (CDCSTOP command ...

Excellent! In that case, I will add that I now have a fully working PAC -- Thanks to BlueBMW -- so I should be able to do minor testing should the need arise. Otherwise, I await the continued dumping efforts of Nemesis.

Well, I was wrong: in fact, running opcode by opcode does not make any good, the only thing that somehow made it go past the black screen on startup was to significantly increase either the number of SUB-CPU cycles executed per line (I forgot I still had this slightly modified in my previous test ...

So what you mean is that there is actually two values for DMNA, the one that can be read and the one that is written ?
Yes, I would say there are different values across the board.

As far as reads go:
- RET and DMNA in 2M mode reflect the wordram assignment as usual.
- RET bit in 1M mode reflects ...

I also have a question regarding Word-RAM and mode switching: to which part is assigned Word-RAM when switching from 1M to 2M mode ? I assume that if RET bit is set as well, it is set to MAIN-CPU side but is it the default ? What if RET bit is not set when MODE bit is changed from 1 to 0 ...

That would be correct if that was to describe 32x32 mode - you need 4 horizontal 8x8 tiles to get 32x32 pixels.

However, to make 16 horizontal pixels, you would need four 4x4 tiles. Hopefully any of that made sense.
That would make a whole lot more sense if there was such a thing as a 4x4 tile ...

The stamps themselves are NOT laid out like tiles in the MD - the 16x16 stamp is actually laid out as sixteen 4x4 tiles. Each tile is like this
0 1 2 3
4 5 6 7
8 9 A B
C D E F
That doesn't sound right. Those should be 8x8 tiles (according to the manual).

Otherwise, your description of the layout ...

(Tasco, your pac ended up being a LOT worse than it originally appeared to be! I'll get you pics later on. Dont worry, it'll be good when I'm done :) )
Cool. You are the man! Can't wait to see. ;)

Also, I had a thought... It might be better to tap the LD video before it even reaches the chip ...