SpritesMind.Net

Can you post compiled versions of updated tests?

The IR problem is in unidirectional. So, all emitting devices doesn't to know about each other. If they can be bidirectional, they can be in passive mode and answer only when base unit ask any single device wich will have unique address (callsign). All arbitrage done by base unit and no colisions wi...

Sure. The joypad sends its own state every X time. Always when any button is pressed. The base reads the joypad state and convert it to state of internal joypad, that physically connected to the console. If no state was recieved by IR after X time (plus some time) the internal joypad state force to ...

Sik wrote: ↑

Thu Aug 17, 2017 8:30 pm

matteus wrote: ↑

Thu Aug 17, 2017 1:39 pm

From Address 003ee4e0 to 00effff0 its nothing but "00"

The end of the ROM should be 003FFFFF =P

The ROM windows should be $000000-$3FFFFF, but ROM itself not required to be up to $3FFFFF.

Ah, so...


Should work! One more reason to use low byte D7-D0.

Then I suppose if neither CAS0, WRL or WRH is asserted an invalid address exception is launched, right? You should use these signals only with CE0 and get desired access within $000000-$3FFFFF (first 4 Mbytes) dedicated to ROM cartridge. That's why 32MBit games use bank switching for SRAM (f.e. Sto...

It is more than meets the eye. If you use D7-D0, so that you can access to it bytewise at odd addresses, because of big endianness of M68K. But MD cartridge slot have only one CAS0 for read and two WRL and WRH for write. So, cartrige can be read only by word while can be written by any byte separatl...

I recently bought SEGA IR joypads. The base: MODEL No. MK-1648 Chipset: SEGA 315-5714 (codes 9338EP713 069 ) http://savepic.net/9631729m.jpg http://savepic.net/9622513m.jpg http://savepic.net/9621489m.jpg http://savepic.net/9620465m.jpg http://savepic.net/9627633m.jpg http://savepic.net/9632753m.jpg...

$1B0 - 'R' $1B1 - 'A' $1B2 : ___ D7 always 1, ___ D6 - 1 = RAM don't destroy after power off, ___ D5 - always 1, ___ D4:D3 - 00 = word sized RAM (D0-D15), 01 = not used, 10 = even byte RAM (D8-D15), 11 = odd byte RAM (D0-D7), ___ D2:D0 - always 000. $1B3 - ' ' (0x20) $1B4 - dword, start address of ...

Oh, so... OK, I can try this at home.

KanedaFr wrote: ↑

Fri Jul 21, 2017 2:00 am

I was waiting for your proto

Like this?

KanedaFr wrote: ↑

Sun Jul 02, 2017 10:16 pm

nothing, only wanted to know if the I2S was as great as it seems (with sound save)

I could not get him to decode I2S as a sound. Only as data.

It's quiet down here. Too quiet.

This is normal practice. This table can be used by downloadable software. And these vectors will always be true, even if the system software is updated.

Exactly.

so bad the 16channels costs 3x the 8channels version It is because 8x is only simple Cypress controller and it support only 24MS/s. 16x contain FPGA and can up to 100MS/s with 1 channel. So it is still cheaper than other LAs. I bought for $37 (more than year ago) . The cheapest LA in 16ch streaming...