Search found 81 matches

by Graz
Mon Dec 07, 2009 12:36 pm
Forum: Megadrive/Genesis
Topic: Neo Myth Menu beta
Replies: 36
Views: 8726

Hi Chilly, It's tough to be certain without being able to play around with the code. I think I may know where some of your performance is going. The filesystem code calls disk_readp repeatedly when doing things like getting directory lists. The sector is always the same between calls, but you always...
by Graz
Sat Oct 31, 2009 5:06 pm
Forum: Blabla
Topic: More 315-5313 unknown stuff (speculation)
Replies: 52
Views: 25227

Jorge Nuno wrote:I will update the pictures along with the development of the schematics
I know this is a pretty ancient thread, but did anything ever come of this?
by Graz
Mon Sep 14, 2009 11:32 am
Forum: Super 32X
Topic: 32X BIOS on MD side
Replies: 6
Views: 3993

Really? By writing some 8 values to $A130F1? That's not what this code does: ROM:000000E8 loc_E8: ; CODE XREF: ROM:000000EEj ROM:000000E8 move.b (a0)+,(a1) ROM:000000EA adda.w #2,a1 ROM:000000EE dbf d7,loc_E8 It writes 8 values to 8 addresses, each two bytes apart - $A130F1, $A130F13, $A130F5, etc....
by Graz
Wed Aug 26, 2009 11:29 am
Forum: Megadrive/Genesis
Topic: newbie's questions
Replies: 35
Views: 9338

That's really strange.

Code: Select all

VDP_setTile(APLAN, 1<<13^130, 3, 10);
Should be exactly the same as

Code: Select all

VDP_setTile(APLAN, 130+(1<<13), 3, 10);
The same is true of operator |. Are you sure something else wasn't out of place?
by Graz
Sat Aug 15, 2009 6:04 pm
Forum: Demos
Topic: SEGA GENESIS VGM PLAYER
Replies: 48
Views: 30947

mic_ wrote:I've implemented a dictionary-based compression scheme now that usually works better than the run-length compression (sometimes much better).
Nice work. What kind of compression ratios are you getting from your new dictionary based approach?
by Graz
Tue Aug 11, 2009 12:18 am
Forum: Super 32X
Topic: DMA to PWM
Replies: 43
Views: 16825

I applied my new found knowledge to the problem and now have perfect playback - sounds great. Just to recap, in case anyone like me stumbles across this years from now... Set Cycle Register (0x20004034 on SH2) to base clock / sample rate Send unsigned PCM data scaled to 1 to (Cycle Register - 1) to ...
by Graz
Mon Aug 10, 2009 12:46 am
Forum: Super 32X
Topic: DMA to PWM
Replies: 43
Views: 16825

Yes, that does sound extremely simple - perhaps it's the quality of the explanation (um, thanks). It all makes sense new. Wow, do I feel dim. I'll give this a spin in a day or so and see what I get.
by Graz
Sun Aug 09, 2009 8:34 pm
Forum: Super 32X
Topic: DMA to PWM
Replies: 43
Views: 16825

Ok, so I tried my original code in Kega using the slave and it works. I still need to find a way to generate PWM data. If anyone has any code to generate PWM data or a better explanation of how to create it than that in the docs, it'd be great if you could post it.
by Graz
Sun Aug 02, 2009 6:22 pm
Forum: Super 32X
Topic: DMA to PWM
Replies: 43
Views: 16825

PWM DMA works... on the slave, not the master. Argh! I've only been using the master! Still haven't had any success, but I don't have time to check anything else right now. I'll move to the slave when I get a chance in a week or so. BTW, does anyone have the utility that converts AIFF to PWM sample...
by Graz
Sat Aug 01, 2009 3:09 pm
Forum: Super 32X
Topic: DMA to PWM
Replies: 43
Views: 16825

I've been testing on emulators so far. I had been using GensKMod until I realized that it didn't support DMA. I've also tried Gens/GS and Kega. I guess I'll stick to real hardware from now on. PWM sound seems to work in every game I've tried on Gens, so I guess not too many use DMA. Does anyone know...
by Graz
Fri Jul 31, 2009 11:56 am
Forum: Super 32X
Topic: DMA to PWM
Replies: 43
Views: 16825

Yes, I've set the cycle and control registers. Writing directly to the PWM FIFO works. I haven't set the mono bit you mentioned, but I have tried DMAing to just the left or right channel with similar results.
by Graz
Fri Jul 31, 2009 12:25 am
Forum: Super 32X
Topic: DMA to PWM
Replies: 43
Views: 16825

DMA to PWM

I'm trying to get DMA to the PWM controller working and am having no success. Here is what I am doing: SAR1 = source address (in ROM, SH2 address space) DAR1 = mono pulse width register (0x20004038) TCR1 = 1024 (some number long enough that I'd notice the output) CHCHR1 = 0x14E1 (fits Sega's 00XX 01...
by Graz
Tue Jul 21, 2009 11:49 am
Forum: Super 32X
Topic: Shared Memory
Replies: 16
Views: 6281

Right, I see. I did some more reading and some experimenting and I think I get it now. Here's how I understand things: 68K communicates destination address and length to SH2 somehow (maybe through communication registers or though the 68K DMA dest registers). SH2 writes destination address and lengt...
by Graz
Mon Jul 20, 2009 11:01 pm
Forum: Super 32X
Topic: Shared Memory
Replies: 16
Views: 6281

Ok. Can the DMA read from the 68K's RAM?
by Graz
Mon Jul 20, 2009 11:45 am
Forum: Super 32X
Topic: Shared Memory
Replies: 16
Views: 6281

Actually, I was planning to put commands and data into a buffer in memory and then write the offset of that buffer into the comm port. This triggers an interrupt which causes the SH2 to act on that data and update it's read pointer (another comm port register). 16 bits per transfer isn't enough. I g...