Search found 864 matches

by Eke
Sat Apr 27, 2019 8:48 pm
Forum: Mega/SegaCD
Topic: Questions on writing a new Mega CD emulator
Replies: 114
Views: 37377

Re: Questions on writing a new Mega CD emulator

Now, about CDC CDC interrupts: these appear to be an amalgamation of four interrupts. DECI = decoder, DTEI = date transfer end, CMDI = command buffer not empty, SYEIN = sync ... something. It's not documented. I don't know anything about the later or where you get that from but I doubt it exists, IF...
by Eke
Sat Apr 27, 2019 12:30 pm
Forum: Mega/SegaCD
Topic: Questions on writing a new Mega CD emulator
Replies: 114
Views: 37377

Re: Questions on writing a new Mega CD emulator

I've seen people say they mirror every $40 bytes and every $200 bytes. That they only map to a120xx/ff80xx or that they map to a12000-a12fff/ff8000-ffffff. Main-CPU side was verified by Charles (see http://gendev.spritesmind.net/forum/viewtopic.php?f=5&t=1276. Afaik, bus arbiter use VA23-VA8 for de...
by Eke
Sat Apr 27, 2019 8:29 am
Forum: Mega/SegaCD
Topic: Questions on writing a new Mega CD emulator
Replies: 114
Views: 37377

Re: Questions on writing a new Mega CD emulator

I will try to answer some of your questions later since I faced similar interrogations when adding Mega CD support in Genesis Plus GX but regarding pending int being cleared when disabled, that's something that was needed in Genesis Plus GX to fix some games freezing in some cases (hence the comment...
by Eke
Sat Apr 27, 2019 6:42 am
Forum: Megadrive/Genesis
Topic: Z80 bus + I/O mapping redux
Replies: 7
Views: 4901

Re: Z80 bus + I/O mapping redux

That's a lot of questions and they adress so many different things... I guess I will pick this one But if a game writes to byte to a10002, what happens? The 68K used in the Genesis per 68000UM.pdf states that D8-D15=D0-D7 for byte writes, and that A0 isn't used. Do the I/O ports bother to check /LDS...
by Eke
Thu Dec 13, 2018 6:25 am
Forum: Controls
Topic: Every peripheral ID?
Replies: 6
Views: 3589

Re: Every peripheral ID?

The numbers (1-8) actually refer to panel number in Activator manuals: 1 corresponds to the panel in front of the player then, in clock order, 2, 3, etc One of the manuals can actually be still found here: http://www.segakore.fr/media/segakore/downloads/systemes/activator_game_guide_u.pdf From my ol...
by Eke
Sun Nov 25, 2018 9:09 am
Forum: Sound
Topic: New Documentation: An authoritative reference on the YM2612
Replies: 859
Views: 478191

Re: New Documentation: An authoritative reference on the YM2612

Nemesis tested the address/data ports relation some years ago http://gendev.spritesmind.net/forum/viewtopic.php?f=24&t=386&start=410 It turns out that writing to an address register stores both the written address, and the part number of the address register you wrote to. You can then write to eithe...
by Eke
Mon Nov 19, 2018 8:25 pm
Forum: Megadrive/Genesis
Topic: Looping access from 68K and Z80
Replies: 25
Views: 10786

Re: Looping access from 68K and Z80

if 68K->Z80->68K was access thought buses it will lock the system at any access not only on VPD access, correct? As said previously, ZA15 is forced low when 68k is accessing Z80 bus so it's not possible to access 68k bank in Z80 memory map upper area ($8000-$FFFF) from 68k since it becomes a mirror...
by Eke
Sun Nov 18, 2018 8:15 pm
Forum: Megadrive/Genesis
Topic: Looping access from 68K and Z80
Replies: 25
Views: 10786

Re: Looping access from 68K and Z80

Well, I/O chip only connects VA1-VA7 and ZA1-ZA7, the rest of address lines are managed by the Bus Arbiter so the most logical is that it sets ZA0 according to !LDS, ZA8-ZA14 with VA8-VA14 and simply forces ZA15 low to prevent access to Z80 bank area, just like it sets VA15-VA23 with bank register s...
by Eke
Sat Nov 17, 2018 5:25 pm
Forum: Megadrive/Genesis
Topic: Looping access from 68K and Z80
Replies: 25
Views: 10786

Re: Looping access from 68K and Z80

Taken both quotes together, it sounds more like the 68000 map decodes mirrors of A00000 for z80 ram, and mirrors of A04000 for FM, and nothing else. He's not sure it does anything at all for the bank address, and freezing for VDP space could just be the mapper not asserting DTACK for an unmapped lo...
by Eke
Fri Nov 16, 2018 11:12 pm
Forum: Megadrive/Genesis
Topic: Looping access from 68K and Z80
Replies: 25
Views: 10786

Re: Looping access from 68K and Z80

Z80 32KB address space is mapped to A0xxxx on 68K. Can Z80 access to its own space using A0 page in upper 32KB? Will it stop 68K while access itself address space because it uses outer loop through 68K? The same opposite question: Z80 has special map of VDP+PSG to 7Fxx address. Can 68K access VDP/P...
by Eke
Mon Oct 15, 2018 8:39 pm
Forum: Megadrive/Genesis
Topic: Bus Arbiter and IO Chip Access
Replies: 28
Views: 13406

Re: Bus Arbiter and IO Chip Access

I think it's just you are not talking about the exact same thing. EDCLK pattern is definitively 15 pulses at MCLK/5 followed by 2 pulses at MCLK/4, this can still be seen in Tiido pictures, even the second one where he observed pixels with 9 MCLK cycles . Pixel clock (SCLK) pattern is different beca...
by Eke
Mon Oct 15, 2018 9:07 am
Forum: Megadrive/Genesis
Topic: Bus Arbiter and IO Chip Access
Replies: 28
Views: 13406

Re: Bus Arbiter and IO Chip Access

VA0 has neither a 315-5339 nor a 315-5345, but instead has an EDCLK generator made out of 74-series logic on a daughter board . There's also at least one 74-series chip on the main PCB between the work RAM chips (presumably for the A14/OE fixes for SMS/MarkIII mode). I know yes, what I meant is tha...
by Eke
Thu Oct 11, 2018 9:15 am
Forum: Megadrive/Genesis
Topic: Bus Arbiter and IO Chip Access
Replies: 28
Views: 13406

Re: Bus Arbiter and IO Chip Access

SCBR is generated by the VDP so it's probably an input. Interestingly, this signal isn't connected to the 5364 chip in the VA3 at all. It just goes straight from the VDP to the color encoder. Actually, are you sure this is actually SBCR (connected to VDP pin 50) and not VCLK (connected to VDP pin 4...
by Eke
Wed Mar 07, 2018 1:05 pm
Forum: Video Display Processor
Topic: Tectoy's weird VDP behavior
Replies: 24
Views: 11650

Re: Tectoy's weird VDP behavior

The new tilemap data snaps in entirely during one frame, as if the fifo was massive, but I can't think of any reason for the delay. That is most likely the case, the clone is probably using a much larger FIFO (or a VRAM cache). Remember that: 1) DMA will release 68k bus and software execution as so...
by Eke
Tue Oct 24, 2017 3:01 pm
Forum: Sound
Topic: New Documentation: An authoritative reference on the YM2612
Replies: 859
Views: 478191

Re: New Documentation: An authoritative reference on the YM2612

Some more news about YM2612 DAC "ladder" effect: a guy named Nuked who analyzed YM3438 die shots recently wrote a cycle-accurate implementation in C and figured the effect was actually caused by two things: 1 ) the fact that the resistor array would not exactly reach Vcc/2 on either negative or posi...