SpritesMind.Net

Hello @srg320, and thank you very much for you quick answer.
Are you telling me that the custom internal ROM ($00~$FF) is actually ... RAM ?

Sorry to relive a topic - again !,
but there is one line of code that I find surprising.
Just between SDER and TV Mode Check, we have
move.l #$8802A2,$70 ; 21 FC 00 88 02 A2 00 70
If my 68k isn't too rusty, I translate this by
"write the value 0x8802a2 ... in ROM ?!"

First of all, how is it ...

Sorry to resurrect such an old topic, but I thought the work I've recently done one the BIOS disassembly would be useful.
Now, it compiles with asmsh /ol!

DC.L resetPC ; Power-on reset PC
DC.L $06040000 ;Power-on reset SP
DC.L resetPC ; Manual reset PC
DC.L $06040000 ;Manual reset SP
DC.L ERR ...

ob1 wrote: Mon Mar 12, 2007 8:34 am ASMSH adds a silly header and appends a byte to the binary. I've written this tool to fix it :

or you could, you know, use "/p"

Thank you.
I have retrieved the DDK.
Though it seems to use all the 32X resources, the SH2 DEI seems left untouched.
Indeed, I found no trace of something like "MOV.*_DMAVECTORN0", _DMAVECTORN0 being the label of DMAVCR0.
Plus, the only value for CHCR I found excluded the IE bit.

So, I guess it's ...

Yo guys.

Here is a disassembly of the Slave SH2 BIOS.
I went a bit further than for the master (13 years ago !!!) and I finally got the frame buffer read (it's for the Sega CD32X, stupid!).

INITIAL_SP equ $0603F800

dc.l start
dc.l INITIAL_SP
dc.l start
dc.l INITIAL_SP

dc.l fail
dc.l 0
dc ...

- is DEI implemented in any emulator ?


Regarding Gens 2.15.4, it looks like it is not implemented.
In sh2a.asm, line 5736 :
ALIGN32

; void FASTCALL SH2_DMA0_Request(SH2_CONTEXT *sh2, UINT8 state)
; ecx = context pointer
; edx = request line for external (0 = off, !0 = on)
;
; RETURN ...

Hello fellows.
The Hitachi SH-7604 Hardware Manual defines the IE bit (bit #2) in CHCR register (§9.2.4) as :
Interrupt Enable Bit (IE): Determines whether or not to request a CPU interrupt at the end of a DMA transfer. When the IE bit is set to 1, an interrupt (DEI) request is setnt to the CPU ...

Once upon a time, Chilly Willy said :

When doing 68K to 32X DMA via the FIFO in the 32X, it has a tendency to lose data randomly. Specifically, the DREQ fails to trigger the DMA under unknown circumstances, which means the SH2 DMA stops. If you are checking the FIFO full flags, it will "stick" at ...

I'm a simple man.
I see more than 64 colors on screen, I thumb-up.

Good luck to you

I'm not sure that I understood everything,
but I have played a few times with HInt, and I must say this rock stable image is great.
Bravo for this piece of work.

Even better, the schematics :

https://console5.com/wiki/File:Mega_Dri ... eet_1).png

I'm not sure I correctly understood your question, but there is this block diagram that I like very much :
https://gamesx.com/wiki/lib/exe/fetch.php?media=schematics:genesis_block_diagram.png
(this diagram states that the address bus is 16 bits, but I'm pretty sure it is 24 bits).
Here, you can ...

Wow! Impressive AND original.
I'll keep an eye on it.
Kudos to you and good luck ^^

Olivier

Thank you so much Kaneda for ensuring this great forum is still up and running.