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But frequency of H-Interrupt and V-Interrupt are more important too?
I always thought these interrupts depended of the position of the TV electron beam?

The H-Int register is decremented every line.
When his valor is < 0, an interrupt is generated.
So if you put 0 in H-Int Counter, you have an interrupt evry line, with 1 every 2 lines ...

Thank you Eke for all this information.
I understant now more precisely how the vdp work :-)

I expect Jorge will make same measure for PAL Timings :-)

If you overclock the vdp, the pixel clock is overclocked too, so the pixels are generated more quickly, so the frame displayed on the screen is ...

Thank you for all this info Jorge.

When you say :

Line 31 (in NTSC) is the first VDP-drawn line.

Does it means that V-Counter not = 0 when the first line is drawed?

Yes i made error with my calculs.
I calculated Number of Master Cycles correctly but not converted in good number of H32 pixels, so i correct them in my post.

Hblank period is composed by end of HSync + start of front porch + end of front porch + front border, wich correspond to 147 MCLks?
So the 7 ...

isn't it 147 EDCLK acoording to your values?

And :

87*4 + (147 - 87) * 5 = 648 MCLKS?

So in theroy for H32 mode :

8 (back border) + 18 (back porch) + 7 (start of Hsync) = 53 EDCLK = 26 "H40 pixels" = 212 MCLKS = 42,4 "H32 pixels"
(Corrected after Eke post : 212/10 = 21,2"H32 pixels")

57 (end ...

So according to Charles MCDonald, HBlank period is 10 pixels in H40 mode wider than in H32 mode (E9 - E4 = 5; 5 * 2 = 10 pixels) ?

So 69 or 70 pixels = approx 552 MClks in H40 mode (69 * 8 = 552) ?

Another question :
In Jorge timing post, when you calculate timings, you said that in H40 mode there ...

I think my Hblank period is too long.
Does the hblank period takes only 644 MClks (92 Clks) instead of 860 Mclks?
The overscan period is not included in hblank area?

The problem i have with sonic 2 is due to the timings i use :

H-INT : 0
HBlankStart = H-INT + 130 MClks
HBlankEnd = H-INT + 130 MClks + 860 Mclks

So the delay between H-INT and HBlankEnd is 990 MClks
The 68K needs 44 Clks (308 Mclks) to fetch registers before executing first instruction of the ...

I'm trying to adjust my DMA Timings with sonic 2 but i have a problem because the display isn't switch off at constant line.
Sometimes it's disabled at line 107 or sometimes at lines 108.
So the blue bar isn't fix ...

I have another question about DMA Timings.
Is it necessary to emulate dma transfert line per line or making all the transfert at start of dma and set the status flag to 0 after necessary cycles is sufficient?

So for exact timings you have something like this :

H-INT + 000 Mclks : H-Sync
H-INT + 130 Mclks : HBlank Start
H-INT + 252 Mclks : Registers fetched, render line
H-INT + 308 Mclks : 68k executes first interrupt instruction if interrupt occured.

Do you agree?

This week end i made tests with this timings.
All games seems to work correctly.

To resume :
- Line rendering at HBLANKSTART + 36 cycles 68k
- Correct c68k core. Now 68k return 44 cycles before executing first instruction. So the first instruction of interrupt process is executed at HBLANKSTART ...

This week end i made tests with this timings.
All games seems to work correctly.

To resume :
- Line rendering at HBLANKSTART + 36 cycles 68k
- Correct c68k core. Now 68k return 44 cycles before executing first instruction. So the first instruction of interrupt process is executed at HBLANKSTART ...

Another thing :

In genesis plus, when border color is modified during Hblank you make a remap of the current line.

But if Cram is modified between the moment the line is rendered and the moment the border color is changed the Cram change will be taken in account?