Search found 230 matches

by mickagame
Thu Nov 14, 2019 10:44 pm
Forum: Megadrive/Genesis
Topic: DMA and FIFO
Replies: 11
Views: 5884

Re: DMA and FIFO

Another question : what happen if the Z80 request the M68000?
The M68000 stop to execute opcode or it continues until it have to do a memory access (and at this moment it wait that the busreq line be back to 1)?
by mickagame
Tue Nov 12, 2019 7:43 pm
Forum: Megadrive/Genesis
Topic: DMA and FIFO
Replies: 11
Views: 5884

Re: DMA and FIFO

That confirm what i had in my mind ...
Thanks Sik !
by mickagame
Tue Nov 12, 2019 6:18 pm
Forum: Megadrive/Genesis
Topic: DMA and FIFO
Replies: 11
Views: 5884

Re: DMA and FIFO

I have a question about the control and data ports of the genesis.
Are these ports inside the vdp chips?
Often in emulator code these ports are outside the vdp code file.
by mickagame
Wed May 08, 2019 2:02 pm
Forum: Megadrive/Genesis
Topic: I'm officially building a microcode-level 68000 core
Replies: 43
Views: 22014

Re: I'm officially building a microcode-level 68000 core

Impressive work nemesis i will read all your documentation with much interest !
by mickagame
Tue Sep 18, 2018 9:00 am
Forum: Hardware
Topic: Some questions about Saturn HW
Replies: 25
Views: 12272

Re: Some questions about Saturn HW

The SH2/VDP1/VDP2/SCU clocks are generated by a PLL (IC20), which uses 14.318MHz * 2 = 28.6 MHz in 352px mode. In 320px mode, it runs the frequency through a 1708/1820 divider to get 26.8MHz. SCU DSP runs at half of that. In PAL units it uses a 17,734 MHz crystal and it is run through a 910/1135 di...
by mickagame
Mon Sep 17, 2018 2:43 pm
Forum: Hardware
Topic: Some questions about Saturn HW
Replies: 25
Views: 12272

Re: Some questions about Saturn HW

Thanks for this complete answer ! So it could be possible to overclock the saturn but not without affecting video signal?
by mickagame
Sat Sep 15, 2018 9:19 am
Forum: Hardware
Topic: Some questions about Saturn HW
Replies: 25
Views: 12272

Re: Some questions about Saturn HW

Hello everyone.

I'm taking benefits of this post to ask a a question about saturn hardware.
How is handle the SH2 clock?
The SH2 generates its own clock and output it to the vdp?
SH2 takes an input clock derived from a master clock (like the 68000 is Master Clock / 7 for a sega genesis)?

Thanks !
by mickagame
Thu May 26, 2016 12:26 pm
Forum: Video Display Processor
Topic: VDP VRAM access timing
Replies: 36
Views: 28947

Re: VDP VRAM access timing

If i undst good the shema from Nemesis : Slot 12 : When Hsync go high the line start to be drawn on tv Slot 6 to 13 : The first left scrolled 2 cells are fetched and output to internal line buffer => During this period 2 cells fulling with background color are output to tv (left border) Slot 14 to 2...
by mickagame
Sun May 08, 2016 5:34 pm
Forum: Megadrive/Genesis
Topic: Genesis Vdp Global Documentation
Replies: 2
Views: 2019

Re: Genesis Vdp Global Documentation

Thanks for the links ;-)
by mickagame
Sat May 07, 2016 8:49 am
Forum: Megadrive/Genesis
Topic: DMA and FIFO
Replies: 11
Views: 5884

Re: DMA and FIFO

Thanks for your answer.
Does the latency affect the dtack signal from vdp to 68K when perform a read or write operation?
by mickagame
Fri May 06, 2016 3:50 pm
Forum: Megadrive/Genesis
Topic: DMA and FIFO
Replies: 11
Views: 5884

DMA and FIFO

Does The DMA is using the external access slot to transfert data from/to vram?
What happen for example if there is a dma fill or dma copy and the 68k try to access vram?
by mickagame
Wed May 04, 2016 12:33 pm
Forum: Megadrive/Genesis
Topic: Genesis Vdp Global Documentation
Replies: 2
Views: 2019

Genesis Vdp Global Documentation

I would like to know if exist a documentation compiling all informations about the genesis vdp (description of all slot, register latch timing, interrupt timing ...).
by mickagame
Mon Jul 20, 2015 4:06 pm
Forum: Video Display Processor
Topic: VDP VRAM access timing
Replies: 36
Views: 28947

If i take your notes Nemesis. From Access Slot 6 to 13 (2 cells Border) datas from 2 first displayed cells are latched and renderer in a 2 cells buffer. During Access Clots 14 to 21 (2 first displayed cells) pixels are generated from the buffer and during this time datas from displayed cells 3 and 4...
by mickagame
Tue Jul 14, 2015 9:20 pm
Forum: Exodus
Topic: Exodus 2.0 + Open Source Release
Replies: 105
Views: 41951

Hi Nemesis. The debugger of Exodus is very useful to me to program my emulator. Tanks to your work.
by mickagame
Mon Jul 13, 2015 10:51 am
Forum: Megadrive/Genesis
Topic: Question About Sonic 2
Replies: 4
Views: 1741

All works OK now thanks for your help ;-)