SpritesMind.Net

I've released a new version of my Gen/MD emulator. Big change this time is a new UI using the Nuklear toolkit. Unlike the old UI, you can actually change almost all config options through the UI rather than editing the config file. Of interest to developers are some improvements to the VDP debug vie...

Here's a small collection of captures of various types of bus interactions. They are in Open Logic Sniffer Project format. Explanations below: direct_color_dma.olp - Capture of the start of 68K->VDP DMA from one of Chilly WIlly's Direct Color DMA samples (note that !CAS and !RAS here refer to VRAM !...

I am searching hardware level information about the interface with the 68K. Do you know if anybody performed logic analyzer traces showing the timing of the clock and the bus control signals? Yes. 68K clock is always the master clock/7 (unless you count the Teradrive which can also run the CPU at 1...

My breakout boards cam it but sadly the pads for the pins on the chip were just a tad too short. New boards ordered but with the US holiday coming up it’ll be 10-14 days before I get them back. In the meantime, I found a semiconductor seller that had some genesis chips in stock so I picked up a cou...

It would be interesting to verify is there are any differences regarding EDCLK between MD VA1 and late rmodels since it seems VA1 (and likely VA0) is using an earlier version of 315-5345 chip (see 315-5339 description here: http://www.tmeeco.eu/SMD/MD1VA1_315-5339.jpg) which does not use VCLK (and ...

EDCLK: This signal is 0/floating (wasnt a very clean 0) when /SRES, /M3 or /HSYNC are asserted(0). Otherwise it seems to be MCLK/4. (I tested with a 5k signal. Got a 1.25K out. I thought this this should /5, maybe it doesn't like the slow speed?) Does not seem to be affected by anything else. It sh...

Did some probing on my model 1 va2. It has a 5308 arbiter, a 5309 IO chip and a 5345. For what it's worth, we have the schematics for the VA3 . Main difference from your VA2 is that the 5345 (EDCLK generator, probably just a PAL or GAL) has been integrated into the bus arbiter (5308) and given the ...

When writing 8Bit numbers to even addresses, is pin B28 (lower byte write) taken low and pin B29 left high, and for odd addresses B28 is left high and B29 is taken low? Or visa versa? Or does it work differently? !LDSW (B28) goes low (which is the "active" level) for writes to odd addresses and !UD...

Bumping this as I've added a number of additional links to the OP. I'm sure there's stuff I've missed, so feel free to suggest additions here.

I then checked Galibert's microcode dump (see here , or here for all data he has) and confirmed the same thing. Oooh, I didn't realize he had gotten that far with decoding the microcode. I'll definitely have to check that out when I get time. The TL;DR version is: "btst dN,#immed8" shares microcode...

l_oliveira wrote: ↑

Wed Sep 19, 2018 9:11 pm

If it is not done that way, the YM3438 actually fails to work on a lot of games.

Which games? I haven't heard of widespread compatibility issues with the Teradrive (which as I previously mentioned has a discrete YM3438), but I'd happy to test some if you know specific games that have problems.

Sik wrote: ↑

Sun Sep 16, 2018 4:06 pm

This reminds me, the Mega Drive never had a discrete YM3438 (somebody pointed it out to me last night after I had posted >.>).

The Teradrive has an actual YM3438.

Wow, good job with this! Thanks! I always wanted to investigate this hardware more, but never found the time. Still quite a few unknowns if you suddenly find yourself with a bunch of free time :wink: Happy to share test code and/or IDA disassembly projects if that happens (though I know how hard fr...

First, let me start with a big thanks to Nemesis and piroxilin for providing Teradrive disk images and firmware images respectively. Having easy access to software/firmware to reverse was a big help. Now for the info I've figured out: M68K Memory Map (standard MD hardware omitted) 000000 - ??????: B...

You should put a non-zero number after the rs.b/rs.w/rs.l as that's the number of elements of that size you're allocating. Not sure if that's causing your syntax error, but you definitely won't get the right results with zero.