SpritesMind.Net

The I/O ports have 7 pins which can be programmed as input or output, so it's possible to program any protocol you like to exchange data between the machines or even PC parallel port. The achievable bitrate is in tens of KiB/s.

IIRC it's just mirrored, it's also documented in gen-hw.txt

Why not just use as --register-prefix-optional ?

Well even expansion port can't do it, SegaCD has to get away without interrupts to MD's 68k. You are partially right about Z80, partially because it only works in master system mode (one of address lines is then repurposed for Z80 NMI). The only things I can think of is connecting a wire to one of I...

Maybe it's time to lift the ban - times change and people occasionally do too.

I've noticed a donate button - be aware that PayPal doesn't like emulators and has frozen accounts of several emulator authors recently.

l_oliveira wrote: I booted the USA 1.10 SEGA CD ROM this way on a TMSS VA6 MD1.

The unmodified SEGA CD BIOS satisfied the TMSS check and stuff worked correctly.

Nice, wasn't expecting it to handle that as it doesn't have to.

How does the Everdrive work for this case exactly? Maybe by watching address bus and toggling CART_IN during BIOS access? Isn't it the case when a cart is inserted the CD BIOS (the original one in the Mega-CD) gets mapped to 0x40000000 and cart is mapped to 0x00000000 and this swaps around when car...

These are currently fastest Sonic TASes (tool-assisted speedruns) hacked into the ROMs themselves and resynced to play on real hardware. Usually to play a TAS on real hardware, some sort of device is needed to be connected to controller port(s) to feed the inputs, with this any console with a flashc...

If you get another free spot you can post here, I (or someone else) may consider taking it.

EU version also has the shied. Notice some differences on chip markings:
http://notaz.gp2x.de/img/hw/virtua_racing_front2.jpg

I'm now considering taking one as well as it would help with my current project, but not 100% sure as it kind of depends on when it's ready.

So, has anyone investigated the memory mode register? I don't have a logic analyzer, but from looking at spinning loops it seems it has no effect on 68k's bus access timings.

Chilly Willy wrote:Oh, I see. Gaps in the CD address range may also be the best way to handle it.

AFAIK there are no gaps in CD address range, it's mirrored all over the place as upper address lines are simply not connected to expansion port..

It's controlled by /CART (B32) pin on the cart connector only, if it's connected to ground, cart's /CE (chip enable) signal will respond to 000000-3fffff, else to 400000-7fffff.