SpritesMind.Net

It's not the 68K that's causing the delay to be a multiple of 2 cycles in the Amiga.
Yes I wasn't clear enough. It's because an amiga bus operation takes always 2 cpu cycles for each subsystem and each 68k operation is always divisible by two.

Some hardware competes with the 68000 though and ...

I mean, what will be the perfect 68k emulator?
I would say something like this: http://visual6502.org/

At the beginning of the third clock cycle, the state of DTACK is latched is latched. If DTACK hasn't been asserted, this clock cycle repeats until DTACK is asserted. This will loop infinitely ...

If I do, I'll dump the raw data directly online, and then we can compare with the timing in yacht.txt.
sounds good


Sure generating savestates is not that easy, but in my opinion the reduced code complexity is worth it.

savestates
------------
For my last emulator I have waited till cpu thread ...

It's much easier to offer amendments or corrections to a document like this than test everything from scratch.

Sure. No one has time to test it all again. There are a few things I am not sure about.

Things like dummy reads in some opcodes, or 2 cycle gap in execution times of exceptions.

For ...

Keep in mind that yacht is from motorola us patent. The difference is that the microcode listing in yacht is a lot more readable than the original.

You can never be sure if patent describes final 68k revision.
(Biggest difference is DCNT which become DBcc)

Logic Analyzer tests are needed.

For my ...

Nemesis wrote: Ultimately, this is failing because I don't have microcode-level emulation of the M68000 yet.

maybe that could interest you

https://sourceforge.net/projects/portable68000/

I'am interested in each timing related information about the 68000, especially in correct ipl latch timing