SpritesMind.Net

Glad someone is still interested in this! I've been super lazy and haven't updated or cleaned up the code as intended, but the source is available at http://sourceforge.net/projects/teamgenesis/ if you want to dig through it. It's REALLY ugly in some places because I decided to use signed and unsign...

Thanks! I'll run through an emulator later and compare. One thing is we are outputting at ~53 kHz and sampling at 48 kHz, so there's a little bit of data loss there. Not sure how much that would affect it. We shifted everything to a 16 bit output with 14-bits of precision, where I think the Genesis ...

We added the 3 tone channels of the PSG. Sonic makes jumping noises now! We also cleaned up the YM2612 quite a bit. To my ears, it sounds pretty good, but please let me know if you see/hear anything wrong. New video is here: http://www.youtube.com/watch?v=zZyLj1gX0_k . I'll also take requests if any...

Thanks guys! Especially Torlus, thank you so much for some clean, easily modifiable code :D. I'm glad you're still checking in here. As for the board, we're using a Xilinx XUPV5-LX110T through our university. This is definitely overkill, and in fact would have probably been easier through with a DE1...

As mentioned in another post, my group is implementing a full Sega Genesis system on an FPGA. This is built off the fpgagen project by Gregory Estrade (Torlus): http://code.google.com/p/fpgagen/ . We've ported the project from Altera to Xilinx and added an original YM2612 driver and cartridge/contro...

I wish I could, but I'm using an Analog Devices AC97 chip that's internally clocked. As far as I can tell, I can only vary the sampling rate from 7 kHz to 48 kHz by setting a register.

I think that's it! Somehow I had gotten the impression that the FM chip was clocked at VCLK and updated every VCLK/6 cycles, but only spit out an output every VCLK/144 cycles. This makes a lot more sense, and fits with my current implementation. I did know about the time-division multiplexing, but h...

Thanks everyone for your help. It turns out that the FIFO buffer worked better for a single note than multiple ones. The buffer would get filled by the first note, causing the following ones to drop writes. I couldn't really see a way to get around this other than periodically stopping the chip (sam...

Thanks Arbee! The question then is what is this serial output stream supposed to consist of? If it's the channel output sampled at 53 kHz, the stream is too fast and I only hear a short "ding" from the speakers. If it is supposed to be the channel output (which updates at 1.27 MHz) extended into a 5...

Hey guys! First post here, but I've been reading this forum for a few months. This site has been a fantastic resource, and I thought I'd pop in with a few questions :) I'm implementing an FPGA version of the Genesis for a class project (building off of Gregory Estrade's project http://code.google.co...