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That makes more sense. Thanks! I’m no where near looking into VDP stuff just yet so I’m sure there will be a ton of rediscoveries.

(that thread was actually one of the first I think where VDP signals behavior was deeply studied, too bad most of the image links are broken now) It's pity, yes. Feel free to ask me to recapture any of it (or any other) with any of this method: oscilloscope with up to 4 channels (up to 100MHz throu...

I know someone who did a pinout of the VA0 EDCLK circuit. I’m asking them for a copy and will run it through a circuit simulator. If anyone knows of a good free simulator with 74LS series parts, let me know. I’ll have to see if our Cadence package has them.

I agree most of the interactions I did with regards to !BGACK should be impossible. I was doing them more to see if it would give more info on how the functionality was implemented at a logic level. I did test with the other signals left asserted when !SRES becomes asserted. With a valid clock it al...

After a bunch of trial and error, and going through every single input in a binary fashion, I think I have a description of how the 315-5345 works. 315-5345 Behaviors EDCLK (9), !EOE (10), IA14 (11) and !NOE(12) are outputs. !BGACK (1), !HSYNC (2), !SRES (3), A14 (4), !M3 (5), !OE0 (6) , MCLK (7) , ...

Actually, I've pulled out the chip entirely and put it on a bread board so I can control everything by hand. But to your point, yes, I’ve slowed MCLK way down to make capturing easier.

Just an FYI, I was using a 536.93 kHz clock for MCLK. Running at 5mhz was radiating too much for me to get clean signals and the function generator didn’t go up past 30mhz anyway.

High Time for Slow Pixel 15 Slow Pixels 2 Fast Pixels
I have some more if you'd like them. Mostly just measuring the widths to make sure they are the same. That pattern of 15-2 repeats as long as HSYNC is asserted.

HardWareMan wrote: ↑

Fri Oct 12, 2018 8:01 am

Feel free to share some pictures.

I took some before I left for work this morning.

Normal EDCLK No HSYNC Start of HSYNC Fast Pixel

... I actually remembered that it is the HSYNC that was the problem. Thanks for this. After setting that one up I was able to see the pattern. I didn’t have enough resolution for discern the exact pattern on my normal scope, so I pulled out my 500MHz 5GS/s one to take a look. The pattern seems to b...

I did a quick check and what I have listed as SBCR is actually VCLK. Funny that the other pinouts I’ve seen online have it as SBCR as well. Guess the majority isn’t always right. LOL. I have a signal generator hereat work and will test with some clocks on MCLK and VCLK and see what behaviors we get ...

So I decided to pull the 5345 chip and wire it up outside the system for testing. Here are the findings thus far although a bit perplexing in places. EDCLK: This signal is 0/floating (wasnt a very clean 0) when /SRES, /M3 or /HSYNC are asserted(0). Otherwise it seems to be MCLK/4. (I tested with a 5...

Did some probing on my model 1 va2. It has a 5308 arbiter, a 5309 IO chip and a 5345. I checked the pinouts on MegaDrive.org and found some inaccuracies. Correct pinout is as follows: 1. /BGACK (connected to BGACK on VDP, 68k and arbiter) 2. /HSYNC 3. /SRES 4. A14 5. /M3 6. /OE0 7. MCLK 8. GND 9. ED...

I am working on an emulator and striving for cycle accuracy. (Aren't we all?) I am attempting to emulate the 513-5433 Arbiter/IO chip. I was wondering if anyone knew of any document or documents that described the behaviors in enough detail to write an emulator for all the involved signals from VDP ...

Thanks for the info. I don’t suppose there are any die shots of the IO chip and Arbiter? That may make things a little easier on me.