Search found 97 matches

by Ti_
Mon Sep 12, 2022 5:59 pm
Forum: Demos
Topic: Cpu speed test rom (md+scd)
Replies: 23
Views: 26425

Re: Cpu speed test rom (md+scd)

Update: + added new mode for Z80: "RAM+ROM" (executing from ram + reading from rom). This results of both M68K and Z80 slowdown. This emulated only in blastem and on fpga's. Other emulators (but not all), does only slowdown for Z80 on accessing rom. The slowdown even happens if M68K executes code f...
by Ti_
Mon Sep 12, 2022 5:12 pm
Forum: Demos
Topic: [Sega MD] various test roms for emu's
Replies: 3
Views: 26080

Re: [Sega MD] various test roms for emu's

Update: Added more tests, some of them requires 100% accuracy. Dma speed test also updated. Thanks ! These are very useful test ROMs ! First time i saw BlastEm failing on that much tests. I don't even speak about Gens who fail everywhere :lol: But current nigthly version of blastem shows best resul...
by Ti_
Mon Sep 12, 2022 5:02 pm
Forum: Demos
Topic: Instruction timing test (68000)
Replies: 8
Views: 8477

Re: Instruction timing test (68000)

Update:
+ added 'privilege violation' and 'trace'.
+ added 'word' variation on ports read/writes tests.
+ added h32 mode for vpd ports read/writes (as separate roms with label _h32).
by Ti_
Sat Aug 20, 2022 5:41 pm
Forum: Demos
Topic: [Sega MD] various test roms for emu's
Replies: 3
Views: 26080

[Sega MD] various test roms for emu's

Two new test roms for emulators, first one - not deeps checks of rarely emulated stuff, second - dma speed checker: some notes: all delays tests not check delay values, only for delay exists or not. sprites over 64 checks how this sprites are work (collision flag used to detect if glitched sprite cr...
by Ti_
Sat Aug 13, 2022 4:27 am
Forum: Megadrive/Genesis
Topic: Undocummented address ranges
Replies: 12
Views: 11523

Re: Undocummented address ranges

I've just finished writing hex-editor-like tool for MegaDrive, to be used for realtime memory inspection: Here are some findings: - memory which has no device associated (open bus) returns next instruction word, but there seems to be some occasional random noise on data lines (here I have 4MB flash...
by Ti_
Thu Aug 04, 2022 7:33 pm
Forum: Demos
Topic: Instruction timing test (68000)
Replies: 8
Views: 8477

Re: Instruction timing test (68000), wip.

Update: + added variations for bclr,bchg,bset on dx, these instructions timing differs if bits (0-15) or (16-31). All emulators ignores this. + values for access to vdp port with display being on now correct for PAL. + removed 'reset' instruction that causes some everdrives carts to reset. + added s...
by Ti_
Mon Aug 01, 2022 7:55 pm
Forum: Demos
Topic: Cpu speed test rom (md+scd)
Replies: 23
Views: 26425

Re: Cpu speed test rom (md+scd)

Here's a *.XLS table with all values:

Also a little update - added variation: "ram+rom" (execute from ram + reading from rom). This gives bigger value than "rom+ram", but lower than "ram" ( 7,440,118 for ntsc, and 7,406,970 for pal).
by Ti_
Tue Jul 19, 2022 8:28 pm
Forum: Demos
Topic: Instruction timing test (68000)
Replies: 8
Views: 8477

Re: Instruction timing test (68000), wip.

Here's an updated rom (only non-sega-cd version) with some extra modes - writing to ram, z80ram, r/w from vram/vsram with disp on, and with unknown commands. Also - if value gets corrected, it's only yellowed, but not changed (extra modes sometimes gives a bit different values). details on unknown c...
by Ti_
Tue Jul 19, 2022 3:14 pm
Forum: Demos
Topic: Instruction timing test (68000)
Replies: 8
Views: 8477

Re: Instruction timing test (68000), wip.

Both sequences are repeated reading with display being off (DISP OFF), but second is more unrolled loop. As for about '11' cycles of port. Test 'don't know' about dram 'refreshes' and cpu frequency. All instructions timing calcuted by relative to others (to add.l d2,d0 and bra.s). Because all instru...
by Ti_
Sun Jul 17, 2022 8:16 pm
Forum: Demos
Topic: Instruction timing test (68000)
Replies: 8
Views: 8477

Re: Instruction timing test (68000), wip.

+ added a bit more instructions.
+ added exceptions instructions.
+ added variation of move.l on vram read/write (duplicates are some unrolled versions).

(some of them not available in sega-cd test version).
by Ti_
Wed Jul 06, 2022 8:54 pm
Forum: Demos
Topic: Instruction timing test (68000)
Replies: 8
Views: 8477

Re: Instruction timing test (68000), wip.

Update - added about 400 instructions variations. added pass/fail/total counter. Now only 2 version of rom - for sega md/emulators, and for sega md with sega-cd. When running on hardware, if instruction test was affected by refresh delay, now it shows in yellow color, and corrected value (no more 'o...
by Ti_
Sun Jun 26, 2022 7:09 pm
Forum: Demos
Topic: Instruction timing test (68000)
Replies: 8
Views: 8477

Instruction timing test (68000)

Instuctions speed test (cycles count for instuction). Not sensitive to CPU speed. Only several instuction done, but more can be easily added. There's 3 rom version: one for emulators, one for hardware sega , and one for sega-cd in mode1. 1) Hardware test has timing values that matches hardware. Some...
by Ti_
Sat Jun 25, 2022 6:47 pm
Forum: Demos
Topic: Cpu speed test rom (md+scd)
Replies: 23
Views: 26425

Re: Cpu speed test rom (md+scd)

Added all modes screenshots for both Pal and Ntsc consoles with sega-cd attached (for v7 version, in previous message). New note, in this screenshots value in mode 'ram+ram', same as in 'ram' (7,488). The value 7,492 from previous message will be if sega-cd is not attached. And it does not affect ot...
by Ti_
Sun Jun 19, 2022 4:04 pm
Forum: Demos
Topic: 1408 colors palette demo (boxes)
Replies: 2
Views: 6250

1408 colors palette demo (boxes)

512 boxes for each type (normal, shadow and highlight)
Screenshot from PAL md2.
by Ti_
Sat Feb 05, 2022 12:06 pm
Forum: Demos
Topic: Cpu speed test rom (md+scd)
Replies: 23
Views: 26425

Re: Cpu speed test rom (md+scd)

Here's an updated version - v7. Added two new modes: (rom+ram) and (ram+ram) for main-cpu. In this modes code executed from ram or rom, but also reads ram, instead of register while counting cycles. This causes yet more slowdowns. We've got some strange results (md1 pcb2 NTSC j rev.va6? + flash chin...