SpritesMind.Net

I've grown to not like environment variables... mainly because I have so many cross compilers that you simply cannot make environment variables to allow them all to work. It's simply not possible.
I don't disagree with defining things in the makefile, but you don't have to put everything in your ...

Those work because the CPU clock is locked to the VDP clock AND you have access to a cycle accurate raster position. The raster position on the Genesis doesn't have the lsb, so you'll never be more accurate than 2 pixels.
The synchronization is done based on the vertical count. The horizontal ...

Note for Saturn SCU: last char in date code is G, therefore it could be as far as revision 6 by the console release. This could be possible as if you read the chip version register, it reads as 00 04. So this thing definitely went through many revivions!
It is my theory that when they wanted to ...

You could try adapting the double interrupt technique used on the C64. Basically you arrange for an interrupt to trigger while the CPU is executing instructions of a known, minimal latency, and then compensate for the single instruction jitter by cycle counting and polling.

Now you're just arguing to hear your own voice.
Same could be said for you. Quoting the documentation (emphasis added): -fschedule-insns
If supported for the target machine, attempt to reorder instructions to eliminate execution stalls due to required data being unavailable.

-fschedule-insns2 ...

Reorder != reorganize.

Chilly Willy wrote:I've seen loop unrolling that did things like that. The sequence of the instructions is "reordered" from the original code (which goes forwards) into code that goes backwards.

That's not what the optimization under question is about.

Reordering is particularly important for delay slots, and after multiplies.
You're right, I had forgotten about the async multiplier.

On non-pipeline processors, reordering is more about bus and register usage than anything else. For example, with the 68000, you could almost do EVERYTHING with ...

Uhh - wouldn't in-order execution CPUs be MORE likely to use scheduling? You want to reorder the instructions manually (by the compiler) for best speed since the CPU doesn't do it in hardware. Scheduling makes no sense for out-of-order CPUs since the CPU is just going to ignore the order anyway and ...

notaz wrote:I've been using -O2 with '-fno-schedule-insns -fno-schedule-insns2' in another project to avoid reordering, but I haven't tested if this works here.

-fschedule-insns attempts to hide the latency of slow instructions by pipeline scheduling, it has no effect on in-order CPUs like 68000 or SH2.

Here's the documentation for the current version of GCC. The inlining thresholds has been tweaked back and forth over the years in order to balance performance and space requirements, and there's a couple of command-line parameters you can tweak if you want to.

I changed the optimization level and it worked fine with 4.4.1/2; he argued about volatiles and not needing to change the optimization level, but you can't argue with reality - it works fine with -O1 and doesn't work with -O2, volatiles be damned.
Lowering the optimization level usually just ...

M68K: Check out disk_io.c for the NeoMyth MD menu - it also only works with -O1.
OK, let's stick to this example as it's one I can actually find. Can you point out an instance of the file being miscompiled (source and disassembly)? When compiling with 4.5.2 I could not find any differences in ...

That may be part of the draft, but I can assure you that concrete examples prove that MIPS, SH, and M68K don't follow those guidelines, and the gcc devs only say that different platforms are "encouraged" to abide by the terms, not required.
Please post an example, as I'd very much like to see one.

Volatile statements may not be reordered across each other, that is specified in the language (§6.7.3.6 of the C99 draft standard: "An object that has volatile-qualified type may be modified in ways unknown to the implementation or have other unknown side effects. Therefore any expression referring ...