SpritesMind.Net

Controller data is read by switching TL/TH
You have to switch them an even times.

What would happen if, by mistake, I switch them an odd times?
has the controller somekind of reset-to-defaut-after-X-ns feature ? or will my read be bugged for the rest of the game ?

If you can log every pin, you'll make my day !!
yes, I'm, for now, interesting by the flow on this FFC.

i was planning to remove the faceplate to get access to the pins while power on, not easier ?

Making the log request below ( ), I suddenly realize the sync words are 14 bits
I don't know how they will be converted to 8 bits (14 bits EFM -> 8 bits data)

I have MD1 and I can make some records for you. Oh oh!! Don't say me that, I have a open list ;) I'd like the timing 1/ about the 4 pins related to SubCode - WFCK - EXCK - SCOR - SBSO I really want to see if SCOR is 2 or 1 WFCK long It would be perfect if logging SBSO could help to identify the syn...

Does anyone know any FPGA or CPLD still 5V tolerant ?
It seems they're no longer available

And I'd like to avoid all the 3.3V level converting things...my goal is to increase my MCD life, not to make it commit suicide

It's probably a newb-level question but I should ask it ;) As you know, every input device has its own ID, which make it possible to detect what is connected to each port. What I never understood is how this Peripheral ID is "set" inside the device. By this, I mean there isn't a complex µC or CPLD (...

OK, i know understand the meaning of every pin http://gendev.spritesmind.net/img/tech/megasd/mcd_connector.png with some check about the sucode part, I'm now trying to find how all of this is synchronized... the Communication part is defined by a IRQ every 1/75s (every sector) :arrow: I read an old ...

HardWareMan wrote:Every frame of 98 contains not only subchannel data but left and rigth channel samples. I don't remember how much but I guess 6 of each. 44100 / 75 / 98 = 6. 6 * 2 * 2 = 24 bytes.

Yes , 2352bytes per sector / 98 frames = 24bytes per frame

I assumed it was this basic serialization of each of the 2+96 each subdata....
But the datasheet just killed me !

What's not clear is : Is SCOR high for 2 frame (S0 and S1) or only S1 ......

OOOOOK Another DSP datasheet seems to give me more details http://gendev.spritesmind.net/img/tech/megasd/subcode_S0S1.jpg http://gendev.spritesmind.net/img/tech/megasd/subcode_S0S1_timing.jpg It's not exactly the same (it push Q first, not P) but i think I got it know, based on previous post When S0...

i found this other Sony EFM Demodulator / subcode decoder (CX7933) diagram. http://gendev.spritesmind.net/img/tech/megasd/subcode_block_diagram.jpg It's clearly explain 1/ => shift register (loop) 4/ => the data to be serialized are on the shift register buffer but it still doesn't explain 2/ SCOR =...

It's time for the CXD2500 to give me some headaches ! So, when the DSP finish to write the frame on buffer - WFCK is put to low - first bit of frame subchannel set on SBSO - if it's the first frame of sector, SCOR is put to HIGH and subcode is first byte of the sync word : S0 ..and not P-W - host st...

yes, it's why this one was a problem for me... I didn't see the link between WFCK / LRCK /... and this one

HardWareMan wrote:Again: 384 / 2 / 16 = 12. Because 2 channels with 16bit in each. 12x oversampling for one bit Delta-Sigma DAC.

OK, thanks Hardwareman.
Sorry but your first post was a mistery, like..."yes 12...and so ?"

thanks again

Hi,

i was wondering is the /time range is still there on megacd

So:
- CD : 0 -> 0x3FFFFF
- CART : 0x400000 -> 0x7FFFFF
- extra stuff on cart : 0xA13000 -> 0xA130FF (which trigger the /TIME pin on cart)

Can anyone confirm ?
thanks