I don't know very much about the snes Hardware.
The Sega marketing was focus on the capability for Megadrive hardware to run fast games like Sonic.
Does exist a specific technical feature that make the différence with snes or it could be possible to do these games on s'est?
Search found 256 matches
- Fri Aug 11, 2023 7:00 am
- Forum: Megadrive/Genesis
- Topic: Megadrive vs Snes Hardware
- Replies: 2
- Views: 36707
- Thu Dec 08, 2022 9:11 pm
- Forum: Megadrive/Genesis
- Topic: Vdp Timings
- Replies: 0
- Views: 98783
Vdp Timings
I would like to know if exist a documentation describing when vdp registers are taked in account during the rendering line process (line cycle or slot). For example, if horizontal scroll register is taked in account at x cycle / slot x so modifying register after this time has no effect on the curre...
- Tue May 31, 2022 11:12 am
- Forum: Megadrive/Genesis
- Topic: Questions About Megadrive Chips/Signal
- Replies: 2
- Views: 24158
Re: Questions About Megadrive Chips/Signal
Z80 bus request and reset come from bus chip, using the single data line that is connected to it. Z80 banker also is done by that chip, one bit at a time. Version register with its many bits comes from the IO chip, and !FDC (MCD presence) and region signals also connect to it. IO chip has all data ...
- Tue May 31, 2022 9:43 am
- Forum: Megadrive/Genesis
- Topic: Questions About Megadrive Chips/Signal
- Replies: 2
- Views: 24158
Questions About Megadrive Chips/Signal
1) Version Register is mapped into M68000 space to access some informations : $A10000 $A10001 Version register => Where is located physically this register? In Bus Arbiter Chip? 2) Always in M68000 space : an address can be used to reset Z80 : $A11200 $A11201 Z80 reset => What chips is involved in t...
- Tue May 24, 2022 5:00 am
- Forum: Megadrive/Genesis
- Topic: VPA Signal in interrupt process
- Replies: 7
- Views: 34660
Re: VPA Signal in interrupt process
It coule be interesting. I dont have the material required to do this.
- Sun May 22, 2022 1:38 pm
- Forum: Megadrive/Genesis
- Topic: VPA Signal in interrupt process
- Replies: 7
- Views: 34660
Re: VPA Signal in interrupt process
No i'm trying to understand how it works because i'm trying to emulate this as accurate as possible.
Do you know if the bus arbitrer chips works with an input signal clock or is just made of logical gate setting output signals depending on input signal?
Do you know if the bus arbitrer chips works with an input signal clock or is just made of logical gate setting output signals depending on input signal?
- Fri May 20, 2022 5:33 pm
- Forum: Megadrive/Genesis
- Topic: VPA Signal in interrupt process
- Replies: 7
- Views: 34660
Re: VPA Signal in interrupt process
Thanks Charles. Do you know what make the bus arbitrer release VPA?
1) The Bus arbitrer generate the signal during an amount of time?
2) Or VPA is released when FC1/FC0 goes low again?
1) The Bus arbitrer generate the signal during an amount of time?
2) Or VPA is released when FC1/FC0 goes low again?
- Mon May 16, 2022 4:51 pm
- Forum: Megadrive/Genesis
- Topic: VPA Signal in interrupt process
- Replies: 7
- Views: 34660
VPA Signal in interrupt process
VPA Signal is used during interrupt process by 68000 to use autovector insted vector read on bus. What component on megadrive generate this signal? I guess the signal is driven by 315-5364. When it turns the signal to low? I see that FC0/FC1 goes to 315-5364. I know that in interrupt process 68000 p...
- Sun Mar 07, 2021 5:21 pm
- Forum: Video Display Processor
- Topic: VDP VRAM access timing
- Replies: 40
- Views: 129024
Re: VDP VRAM access timing
Thanks eke step by step all is more clear for me. When you speak about active display you speak about visible display area, not the left border?
- Fri Mar 05, 2021 9:29 pm
- Forum: Video Display Processor
- Topic: VDP VRAM access timing
- Replies: 40
- Views: 129024
- Fri Mar 05, 2021 9:28 am
- Forum: Video Display Processor
- Topic: Megadrive video timings
- Replies: 123
- Views: 177292
Re: Megadrive video timings
Thanks for informations. All is clear now
- Thu Mar 04, 2021 12:53 pm
- Forum: Video Display Processor
- Topic: Megadrive video timings
- Replies: 123
- Views: 177292
Re:
Since most emulators do the DMA immediately anyhow it's not really a concern. My emulator performs more like the real system in that the 68K is frozen and all other components run until the DMA is finished (with the appropriate slots). Since I am using Musashi I needed to handle the case where this...
- Tue Feb 16, 2021 11:47 am
- Forum: Megadrive/Genesis
- Topic: Version Register
- Replies: 6
- Views: 13716
Re: Version Register
Ok thanks for this informations
The value is hardwired inside the chip or come from external (by a jumper for example)?
The value is hardwired inside the chip or come from external (by a jumper for example)?
- Mon Feb 15, 2021 7:05 pm
- Forum: Megadrive/Genesis
- Topic: Version Register
- Replies: 6
- Views: 13716
Version Register
The version register in IO Chip give informations like : Bit(7) : Mode => Pin /LANG from IO Chip (can be set by jumper) Bit(6) : VMode => Pin /PAL from IO Chip (can be set by jumper) Bit(5) : Disk => Pin /DISK from IO Chip Bit(4) : Reserved Bit(3-0) : Version => ??? Is there any signal from IOChip c...
- Tue Feb 09, 2021 8:14 pm
- Forum: Megadrive/Genesis
- Topic: 68K Memory access
- Replies: 9
- Views: 14255
Re: 68K Memory access
When 68K perform long write/read, the 68K in reality do 2 words access.
In what sequence does it?
1) Address + 0
2) Address + 2
Or
1) Address + 2
2) Address + 0
?
In what sequence does it?
1) Address + 0
2) Address + 2
Or
1) Address + 2
2) Address + 0
?