SpritesMind.Net

I don't know very much about the snes Hardware.
The Sega marketing was focus on the capability for Megadrive hardware to run fast games like Sonic.
Does exist a specific technical feature that make the différence with snes or it could be possible to do these games on s'est?

I would like to know if exist a documentation describing when vdp registers are taked in account during the rendering line process (line cycle or slot).
For example, if horizontal scroll register is taked in account at x cycle / slot x so modifying register after this time has no effect on the ...

Z80 bus request and reset come from bus chip, using the single data line that is connected to it. Z80 banker also is done by that chip, one bit at a time.

Version register with its many bits comes from the IO chip, and !FDC (MCD presence) and region signals also connect to it.

IO chip has all ...

1) Version Register is mapped into M68000 space to access some informations :
$A10000 $A10001 Version register
=> Where is located physically this register? In Bus Arbiter Chip?

2) Always in M68000 space : an address can be used to reset Z80 :
$A11200 $A11201 Z80 reset
=> What chips is involved in ...

It coule be interesting. I dont have the material required to do this.

No i'm trying to understand how it works because i'm trying to emulate this as accurate as possible.
Do you know if the bus arbitrer chips works with an input signal clock or is just made of logical gate setting output signals depending on input signal?

Thanks Charles. Do you know what make the bus arbitrer release VPA?
1) The Bus arbitrer generate the signal during an amount of time?
2) Or VPA is released when FC1/FC0 goes low again?

VPA Signal is used during interrupt process by 68000 to use autovector insted vector read on bus. What component on megadrive generate this signal? I guess the signal is driven by 315-5364. When it turns the signal to low? I see that FC0/FC1 goes to 315-5364. I know that in interrupt process 68000 ...

Thanks eke step by step all is more clear for me. When you speak about active display you speak about visible display area, not the left border?

Can someone correct me if i understand the timings in the wrong way?



I wonder if xscroll = 0 what pattern are read during the two first left scrolled cells?

Thanks for informations. All is clear now

Since most emulators do the DMA immediately anyhow it's not really a concern. My emulator performs more like the real system in that the 68K is frozen and all other components run until the DMA is finished (with the appropriate slots). Since I am using Musashi I needed to handle the case where ...

Ok thanks for this informations
The value is hardwired inside the chip or come from external (by a jumper for example)?

The version register in IO Chip give informations like :

Bit(7) : Mode => Pin /LANG from IO Chip (can be set by jumper)
Bit(6) : VMode => Pin /PAL from IO Chip (can be set by jumper)
Bit(5) : Disk => Pin /DISK from IO Chip
Bit(4) : Reserved
Bit(3-0) : Version => ???

Is there any signal from IOChip ...

When 68K perform long write/read, the 68K in reality do 2 words access.
In what sequence does it?
1) Address + 0
2) Address + 2
Or
1) Address + 2
2) Address + 0

?