Search found 230 matches

by mickagame
Wed May 13, 2020 5:13 am
Forum: Megadrive/Genesis
Topic: VDP 8x16 Interlace Mode
Replies: 7
Views: 2112

Re: VDP 8x16 Interlace Mode

Thanks for your answers guys. It make sens.
by mickagame
Tue May 12, 2020 8:16 am
Forum: Megadrive/Genesis
Topic: VDP 8x16 Interlace Mode
Replies: 7
Views: 2112

VDP 8x16 Interlace Mode

Hello everybody.
I'm asking myself why there is not much game using 8x16 Interlace Mode?
Why developper were using 320x240 mode instead of high resolution mode available on the system (320*480)?
by mickagame
Wed Dec 11, 2019 5:27 pm
Forum: Megadrive/Genesis
Topic: M68K Bus Control and Vdp
Replies: 25
Views: 9019

Re: M68K Bus Control and Vdp

Miquel wrote:
Wed Dec 11, 2019 4:20 pm
No word access: Z80 memory space can only be accessed by the 68k in byte address mode, and that has to mean something.
Does that mean that accessing Z80 space in word mode (UDS and LDS selected) does not have any effects? :?:
by mickagame
Wed Dec 11, 2019 6:14 am
Forum: Megadrive/Genesis
Topic: M68K Bus Control and Vdp
Replies: 25
Views: 9019

Re: M68K Bus Control and Vdp

Another question about accessing Z80 space from 68K side : From what i understand : - If UDS selected byte will be read at even adress from Z80 bus (addr + 0) and will be returned at upper byte from 68K Bus (D15-D8) - If LDS selected byte will be read at even adress from Z80 bus (addr + 1) and will ...
by mickagame
Tue Dec 10, 2019 6:43 pm
Forum: Megadrive/Genesis
Topic: M68K Bus Control and Vdp
Replies: 25
Views: 9019

Re: M68K Bus Control and Vdp

68K duplicates high and lwo bytes during 8bit writes (i.e $12 is $1212 on the bus). Reads are aways 16bit and CPU internally chooses which half to use depending on address. That make sens. From design code point of view this behavior have to be in my 68K core code, not in my vdp code. if (addr & 1)...
by mickagame
Tue Dec 10, 2019 6:22 am
Forum: Megadrive/Genesis
Topic: M68K Bus Control and Vdp
Replies: 25
Views: 9019

Re: M68K Bus Control and Vdp

68K duplicates high and lwo bytes during 8bit writes (i.e $12 is $1212 on the bus). Reads are aways 16bit and CPU internally chooses which half to use depending on address. That make sens. From design code point of view this behavior have to be in my 68K core code, not in my vdp code. if (addr & 1)...
by mickagame
Mon Dec 09, 2019 8:05 pm
Forum: Megadrive/Genesis
Topic: M68K Bus Control and Vdp
Replies: 25
Views: 9019

Re: M68K Bus Control and Vdp

From Genesis Plus GX Source : void vdp_write_byte(unsigned int address, unsigned int data) { switch (address & 0xFC) { case 0x00: /* Data port */ { vdp_68k_data_w(data << 8 | data); return; } case 0x04: /* Control port */ { vdp_68k_ctrl_w(data << 8 | data); return; } case 0x10: /* PSG */ case 0x14: ...
by mickagame
Mon Dec 09, 2019 6:53 pm
Forum: Megadrive/Genesis
Topic: M68K Bus Control and Vdp
Replies: 25
Views: 9019

Re: M68K Bus Control and Vdp

I'm talking about the cpu register. When you do read access with upper byte the cpu take the upper byte (D15-D8) from the bus and put this byte into lower byte of register. Now, at the contrary, what happen if you do write access to vdp control port with - UDS selected (<=> write byte at even adress...
by mickagame
Mon Dec 09, 2019 6:02 pm
Forum: Megadrive/Genesis
Topic: M68K Bus Control and Vdp
Replies: 25
Views: 9019

Re: M68K Bus Control and Vdp

From my point of view when uds is selected the 68k put the upper byte of data bus into lower byte of register.
by mickagame
Mon Dec 09, 2019 6:20 am
Forum: Megadrive/Genesis
Topic: M68K Bus Control and Vdp
Replies: 25
Views: 9019

Re: M68K Bus Control and Vdp

Is this the way i emulate my vdp access : u32 Vdp::readWord(u32 adress, u32 ctrl) The method return D15-D0 lines (Word) U32 adress : A24-A1 lines adress (A0 is bit 0 but is ignored) u32 ctrl : Bit 0 : LDS, Bit 1 : UDS Let's take an example of reading upper byte from Control data port from the 68K si...
by mickagame
Sun Dec 08, 2019 1:42 pm
Forum: Megadrive/Genesis
Topic: M68K Bus Control and Vdp
Replies: 25
Views: 9019

M68K Bus Control and Vdp

I have a question about the vdp/68K connection. The VDP is connected to UDS/LDS signal from the 68K. What the consequence for the vdp internally, for example, of reading upper byte (UDS = 0, LDS = 1) of Control/Data or HVC Counter? Does the VDP return only upper byte on the D15-D8 data line and does...
by mickagame
Tue Nov 19, 2019 8:14 pm
Forum: Megadrive/Genesis
Topic: Noob questions: DEFINITIVE info about Z80 BUSREQ, RESET?
Replies: 28
Views: 12994

Re: Noob questions: DEFINITIVE info about Z80 BUSREQ, RESET?

When you assert bus request, what you're doing is asking the Z80 to let its bus alone — which may take a bit of time, since it needs to finish any ongoing access first. You're supposed to read back from $A11100 to know when the Z80 has done that. The problem is that while the Z80 is reset it will n...
by mickagame
Tue Nov 19, 2019 6:32 am
Forum: Megadrive/Genesis
Topic: Noob questions: DEFINITIVE info about Z80 BUSREQ, RESET?
Replies: 28
Views: 12994

Re: Noob questions: DEFINITIVE info about Z80 BUSREQ, RESET?

It's… messier than that: https://plutiedev.com/using-the-z80#loading-z80 Or also from the Sega docs (though it's essentially describing the same thing): Z80 Start-Up Z-80 Operation Sequence: BUS REQ ON BUS RESET OFF 68k copies program into Z-80 S-RAM BUS RESET ON BUS REQ OFF BUS RESET OFF The bigge...
by mickagame
Sat Nov 16, 2019 1:55 pm
Forum: Megadrive/Genesis
Topic: DMA and FIFO
Replies: 11
Views: 6122

Re: DMA and FIFO

Thank you!
by mickagame
Sat Nov 16, 2019 7:59 am
Forum: Megadrive/Genesis
Topic: Noob questions: DEFINITIVE info about Z80 BUSREQ, RESET?
Replies: 28
Views: 12994

Re: Noob questions: DEFINITIVE info about Z80 BUSREQ, RESET?

I'm using this thread to ask a question about Reset et BusAck signals from the Z80.
While the Z80 is resetting (RESET Pin in low state) how is the BusAck Signal?
If the BusAck Signal is low that mean the 68k can read/write the Z80 bus (That what i understand from this post).