Search found 219 matches

by mickagame
Tue Nov 19, 2019 8:14 pm
Forum: Megadrive/Genesis
Topic: Noob questions: DEFINITIVE info about Z80 BUSREQ, RESET?
Replies: 28
Views: 5086

Re: Noob questions: DEFINITIVE info about Z80 BUSREQ, RESET?

When you assert bus request, what you're doing is asking the Z80 to let its bus alone — which may take a bit of time, since it needs to finish any ongoing access first. You're supposed to read back from $A11100 to know when the Z80 has done that. The problem is that while the Z80 is reset it will n...
by mickagame
Tue Nov 19, 2019 6:32 am
Forum: Megadrive/Genesis
Topic: Noob questions: DEFINITIVE info about Z80 BUSREQ, RESET?
Replies: 28
Views: 5086

Re: Noob questions: DEFINITIVE info about Z80 BUSREQ, RESET?

It's… messier than that: https://plutiedev.com/using-the-z80#loading-z80 Or also from the Sega docs (though it's essentially describing the same thing): Z80 Start-Up Z-80 Operation Sequence: BUS REQ ON BUS RESET OFF 68k copies program into Z-80 S-RAM BUS RESET ON BUS REQ OFF BUS RESET OFF The bigge...
by mickagame
Sat Nov 16, 2019 1:55 pm
Forum: Megadrive/Genesis
Topic: DMA and FIFO
Replies: 11
Views: 2112

Re: DMA and FIFO

Thank you!
by mickagame
Sat Nov 16, 2019 7:59 am
Forum: Megadrive/Genesis
Topic: Noob questions: DEFINITIVE info about Z80 BUSREQ, RESET?
Replies: 28
Views: 5086

Re: Noob questions: DEFINITIVE info about Z80 BUSREQ, RESET?

I'm using this thread to ask a question about Reset et BusAck signals from the Z80.
While the Z80 is resetting (RESET Pin in low state) how is the BusAck Signal?
If the BusAck Signal is low that mean the 68k can read/write the Z80 bus (That what i understand from this post).
by mickagame
Thu Nov 14, 2019 10:44 pm
Forum: Megadrive/Genesis
Topic: DMA and FIFO
Replies: 11
Views: 2112

Re: DMA and FIFO

Another question : what happen if the Z80 request the M68000?
The M68000 stop to execute opcode or it continues until it have to do a memory access (and at this moment it wait that the busreq line be back to 1)?
by mickagame
Tue Nov 12, 2019 7:43 pm
Forum: Megadrive/Genesis
Topic: DMA and FIFO
Replies: 11
Views: 2112

Re: DMA and FIFO

That confirm what i had in my mind ...
Thanks Sik !
by mickagame
Tue Nov 12, 2019 6:18 pm
Forum: Megadrive/Genesis
Topic: DMA and FIFO
Replies: 11
Views: 2112

Re: DMA and FIFO

I have a question about the control and data ports of the genesis.
Are these ports inside the vdp chips?
Often in emulator code these ports are outside the vdp code file.
by mickagame
Wed May 08, 2019 2:02 pm
Forum: Megadrive/Genesis
Topic: I'm officially building a microcode-level 68000 core
Replies: 43
Views: 7694

Re: I'm officially building a microcode-level 68000 core

Impressive work nemesis i will read all your documentation with much interest !
by mickagame
Tue Sep 18, 2018 9:00 am
Forum: Hardware
Topic: Some questions about Saturn HW
Replies: 25
Views: 6445

Re: Some questions about Saturn HW

The SH2/VDP1/VDP2/SCU clocks are generated by a PLL (IC20), which uses 14.318MHz * 2 = 28.6 MHz in 352px mode. In 320px mode, it runs the frequency through a 1708/1820 divider to get 26.8MHz. SCU DSP runs at half of that. In PAL units it uses a 17,734 MHz crystal and it is run through a 910/1135 di...
by mickagame
Mon Sep 17, 2018 2:43 pm
Forum: Hardware
Topic: Some questions about Saturn HW
Replies: 25
Views: 6445

Re: Some questions about Saturn HW

Thanks for this complete answer ! So it could be possible to overclock the saturn but not without affecting video signal?
by mickagame
Sat Sep 15, 2018 9:19 am
Forum: Hardware
Topic: Some questions about Saturn HW
Replies: 25
Views: 6445

Re: Some questions about Saturn HW

Hello everyone.

I'm taking benefits of this post to ask a a question about saturn hardware.
How is handle the SH2 clock?
The SH2 generates its own clock and output it to the vdp?
SH2 takes an input clock derived from a master clock (like the 68000 is Master Clock / 7 for a sega genesis)?

Thanks !
by mickagame
Thu May 26, 2016 12:26 pm
Forum: Video Display Processor
Topic: VDP VRAM access timing
Replies: 36
Views: 21297

Re: VDP VRAM access timing

If i undst good the shema from Nemesis : Slot 12 : When Hsync go high the line start to be drawn on tv Slot 6 to 13 : The first left scrolled 2 cells are fetched and output to internal line buffer => During this period 2 cells fulling with background color are output to tv (left border) Slot 14 to 2...
by mickagame
Sun May 08, 2016 5:34 pm
Forum: Megadrive/Genesis
Topic: Genesis Vdp Global Documentation
Replies: 2
Views: 1588

Re: Genesis Vdp Global Documentation

Thanks for the links ;-)
by mickagame
Sat May 07, 2016 8:49 am
Forum: Megadrive/Genesis
Topic: DMA and FIFO
Replies: 11
Views: 2112

Re: DMA and FIFO

Thanks for your answer.
Does the latency affect the dtack signal from vdp to 68K when perform a read or write operation?
by mickagame
Fri May 06, 2016 3:50 pm
Forum: Megadrive/Genesis
Topic: DMA and FIFO
Replies: 11
Views: 2112

DMA and FIFO

Does The DMA is using the external access slot to transfert data from/to vram?
What happen for example if there is a dma fill or dma copy and the 68k try to access vram?