SpritesMind.Net

When you assert bus request, what you're doing is asking the Z80 to let its bus alone — which may take a bit of time, since it needs to finish any ongoing access first. You're supposed to read back from $A11100 to know when the Z80 has done that. The problem is that while the Z80 is reset it will n...

It's… messier than that: https://plutiedev.com/using-the-z80#loading-z80 Or also from the Sega docs (though it's essentially describing the same thing): Z80 Start-Up Z-80 Operation Sequence: BUS REQ ON BUS RESET OFF 68k copies program into Z-80 S-RAM BUS RESET ON BUS REQ OFF BUS RESET OFF The bigge...

Thank you!

I'm using this thread to ask a question about Reset et BusAck signals from the Z80.
While the Z80 is resetting (RESET Pin in low state) how is the BusAck Signal?
If the BusAck Signal is low that mean the 68k can read/write the Z80 bus (That what i understand from this post).

Another question : what happen if the Z80 request the M68000?
The M68000 stop to execute opcode or it continues until it have to do a memory access (and at this moment it wait that the busreq line be back to 1)?

That confirm what i had in my mind ...
Thanks Sik !

I have a question about the control and data ports of the genesis.
Are these ports inside the vdp chips?
Often in emulator code these ports are outside the vdp code file.

Impressive work nemesis i will read all your documentation with much interest !

The SH2/VDP1/VDP2/SCU clocks are generated by a PLL (IC20), which uses 14.318MHz * 2 = 28.6 MHz in 352px mode. In 320px mode, it runs the frequency through a 1708/1820 divider to get 26.8MHz. SCU DSP runs at half of that. In PAL units it uses a 17,734 MHz crystal and it is run through a 910/1135 di...

Thanks for this complete answer ! So it could be possible to overclock the saturn but not without affecting video signal?

Hello everyone.

I'm taking benefits of this post to ask a a question about saturn hardware.
How is handle the SH2 clock?
The SH2 generates its own clock and output it to the vdp?
SH2 takes an input clock derived from a master clock (like the 68000 is Master Clock / 7 for a sega genesis)?

Thanks !

If i undst good the shema from Nemesis : Slot 12 : When Hsync go high the line start to be drawn on tv Slot 6 to 13 : The first left scrolled 2 cells are fetched and output to internal line buffer => During this period 2 cells fulling with background color are output to tv (left border) Slot 14 to 2...

Thanks for the links

Thanks for your answer.
Does the latency affect the dtack signal from vdp to 68K when perform a read or write operation?

Does The DMA is using the external access slot to transfert data from/to vram?
What happen for example if there is a dma fill or dma copy and the 68k try to access vram?