SpritesMind.Net

I try to understand the order of bus transaction in MOVE memory,(xxx).L.

According to https://pasti.fxatari.com/68kdocs/68kPrefetch.html :
When the destination addressing mode is long absolute and the source operand is any memory addr.mode, step 4 is interleaved in the middle of step 3. Step 3 only ...

My test is ok now Thanks

My test is ok now Thanks

This test is making a "address error" exception. These access correspond to push to ssp pc, sr, ir and address access

I finally found the reason.
This is because the test do misaligned access so the cpu have to generate an exception and write at ssp address.

Address Register A3 : 0x3e4d4a5b
+ Displacement (s8) (0xc4f) = 0x4f
===> Result = 0x3E4D4AAA
+ Index d0 : 0xa1e940b7 (No scale for M68000)
===> Result = E0368B61
<=> 0x368B61 (24 bits)
It doesn't correspond to 0x4542aa ... 0x4542a0 area

Hello

I'm working actually on a 68k core that synchronize at each memory access (without threaded mecanism).

I'm stressing my core with JSON Test Suit : https://github.com/SingleStepTests/ProcessorTests

I have problem with this test :

"name": "000 ADD.l D5, (d8, A3, Xn) dbb3",

Initial important ...

I don't know very much about the snes Hardware.
The Sega marketing was focus on the capability for Megadrive hardware to run fast games like Sonic.
Does exist a specific technical feature that make the différence with snes or it could be possible to do these games on s'est?

I would like to know if exist a documentation describing when vdp registers are taked in account during the rendering line process (line cycle or slot).
For example, if horizontal scroll register is taked in account at x cycle / slot x so modifying register after this time has no effect on the ...

Z80 bus request and reset come from bus chip, using the single data line that is connected to it. Z80 banker also is done by that chip, one bit at a time.

Version register with its many bits comes from the IO chip, and !FDC (MCD presence) and region signals also connect to it.

IO chip has all ...

1) Version Register is mapped into M68000 space to access some informations :
$A10000 $A10001 Version register
=> Where is located physically this register? In Bus Arbiter Chip?

2) Always in M68000 space : an address can be used to reset Z80 :
$A11200 $A11201 Z80 reset
=> What chips is involved in ...

It coule be interesting. I dont have the material required to do this.

No i'm trying to understand how it works because i'm trying to emulate this as accurate as possible.
Do you know if the bus arbitrer chips works with an input signal clock or is just made of logical gate setting output signals depending on input signal?

Thanks Charles. Do you know what make the bus arbitrer release VPA?
1) The Bus arbitrer generate the signal during an amount of time?
2) Or VPA is released when FC1/FC0 goes low again?

VPA Signal is used during interrupt process by 68000 to use autovector insted vector read on bus. What component on megadrive generate this signal? I guess the signal is driven by 315-5364. When it turns the signal to low? I see that FC0/FC1 goes to 315-5364. I know that in interrupt process 68000 ...