SpritesMind.Net

This is the right way to do it, there shouldn't be any problems at all.

It has definitely gone quiet over the years... But it has certainly been a ride, I was still a teenager when I first got here, and I'm gonna be 35 in November ! It seems I joined 2006 december, in not such a long time it'll be 20 years :shock: Much of the communications have moved to places like Dis...

This is impressive, even without flipping ! I imagine the forest example could benefit a lot from that.

It is seen in anything that moves horiozntally. Vertically you will get some artifacts too depending on scroll/movement speed as there will be whole lines of GFX missing every other frame and it will be seen among any kind of horizontal line patterns most particularly

There are no access slots in line blanking period, because VDP is busy rendering sprites which uses up all the VRAM bandwidth in that time. You can turn off rendering for the duration and get few tens of bytes worth of VRAM bandwidth but the cost is no sprites on the next line and some garbage sprit...

Game does its logic, which probably finishes before Active scan is finished, then it waits until it does finish and Passive scan starts and does all the VRAM etc. updates, after than it waits for Passive scan to end and Active to start and the whole process repeats. That is the basic structure of th...

Think of it this way : VDP and CPU are two runners on a track, the track has the length of one frame and both of them start at the same time. VDP does different things depending on what distance it has reached on the track and there are two major sections on the track for it : *Active part - where i...

In general you do not count Active lines as part of your budget since that is where your game logic runs and in general games do not try to update VRAM in that time but do their logic, wait for Passive scan to start and then start the necessary transfers. So that 237 tiles is the absolute maximum yo...

Theoretical maximums in each resolution : Number of tiles that can be transferred per frame : +---------+---------------------------+---------------------------+ | | 50Hz | 60Hz | | +-------------+-------------+-------------+-------------+ | | V224 | V240 | V224 | V240 | | +------+------+------+----...

Yes, both fields of a frame are different so the game is effectively 60FPS. The game doesn't have to wait for both fields to finish drawing before starting the next frame, if it did it would have 30FPS. It is like many PS2 and Dreamcast games that run in interlaced mode but are not necessarily locke...

One thing is that the write itself happens at the end of instruction so the delay really starts then and what happens next depends on what comes after. In the end I gave up trying to optimize access speeds and use IX/IY with YMPORT in them permanently, since I don't use them for anything else due to...

I remember needing a larger than normal delay on key on/off registers when I made my sound driver many years ago, the envelope thing you mention is because the 4bits react differently and sometimes one or more won't do same as others and this can dramatically alter the sound. I also remember getting...

I would do it to my machines just beacuse I don't have or are unlikely to ever gonna have the RAM cart, those extra 24KB will be most welcome lol

Z80 bus request and reset come from bus chip, using the single data line that is connected to it. Z80 banker also is done by that chip, one bit at a time. Version register with its many bits comes from the IO chip, and !FDC (MCD presence) and region signals also connect to it. IO chip has all data l...

I think I made a typo and meant to write CXA output instead. Signal levels are near 1Vpp for full while there. It was so long ago so I am not totally sure anymore. MD VDP RGB DAC output is roughly linear when unloaded indeed, but it is quite high impedance and the loading from the divider will cause...