SpritesMind.Net

DMA doesn't cross 128KByte boundaries but wraps around within 128KB block.

It is possible to update DAC once every sample if you have cycle synchronity to the YM. I did some tests where YM and Z80 were made to share the clock in MD and I could get unique samples out every 144 cycles. Doing rates between full and half sample rate are very ugly though due to the "resampling"...

That resistor is the same as 330ohm to ground if it connects to another output, kind of like both outputs driving to a 330ohm load if their states differ (one side high, other low and vice versa). It is a current limit and roughly like lighting up a LED via an IO pin. I'm sure the IO port output dri...

There are 330ohm series resistors on TH and TL or TR lines which will help in cases using those pins out of the normal way. 330 ohms isn't a huge load to fight.

Pins on the controller port can be both inputs and outputs and some devices expect the direction to be set different from what a normal controller configuration uses. If two outputs get connected together you will have one or both sides getting damaged sooner or later.

EDCLK generation is made with a little sub board on MD1 VA0 that consists of 3x logic chip. IA14 is probably made by the 00 chip between the RAMs on VA0. Nobody seems to have made a schematic of the board yet though. Full EDCLK pattern is "8aaaaaaa99aaaaaaa8aaaaaaa99aaaaaaa" where each symbol is one...

EDCLK is an input to the VDP. And now I actually remembered that it is the HSYNC that was the problem. Because of the open drain factor I had problems with my first set of measurements as probe capacitance caused my measurements to be off by several pixels due to rise of the signal getting altered. ...

I only have SE-95 clone chips to test, I haven't tried it though.

EDCLK is open drain, you need a pullup on it.
EDIT: It isn't, but HSYNC is and it is used for EDCLK generation by the Bus chip and it caused me trouble. More details in next post by me.

When you stop the clock of YM2612 it needs to settle in Low state or the chip will get burning hot within 10 seconds or so. I have a project where the clock can be stopped and I noticed the chip getting unusually hot in very short amount of time when the clock was stopped in High state.

Low and high bytes contain same data when doing 8 bit writes.

What is that DC.L doing there ? It will be executed as an instruction which will depend on exact value of _INT.

EPROMs are no more permanent than NOR Flash. Both work on same sort of principle and will degrade in same sort of manner. EPROMs will last less though, 50 years is probably the maximum while most chips I have looked at give 40 year rating. NOR flashes are usually rated for over 100 years.

PCBs aren't a problem, main thing is EPROMs. You can mostly only get pulls, meaning they're been used before and their state is often unknown. Those chips haven't been produced for many years now and eventually the supply will run out, leaving dodgier and dodgier parts left until those are gone too.

Since it would require bus crossing, abitration will take place and one will wait while other finishes, there will not be a bus conflict happening.