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When you play CDDA you lose access to the CD drive more or less so whatever you want to show will have to fit in the RAM, and you have limited amount of that.

I guess it'll work then, I hope there won't be more troubles with the new version ~

I think it would work, assuming flash is fine with its !CE always low. Logic itself should be sound, disregarding any timing issues.

MD2 VA0 and VA1 do not have 75ohm load on the cartslot signals. 32X just has very low output impedance amp that can drive headphones (i.e 16 ohm load), there's no variation in output level due to it. You just need a beefy amp to make things work.

Sik wrote: ↑

Thu Jan 16, 2020 12:44 am

Anyway, if I'm understanding correctly this means the audio output (as far as the cartridge slot goes) is ±2V, excluding bias?

Yup, +/-2V into 75ohm load is the target for cartslot audio.

The clipping is due to the mixing+amp chip, it isn't rail-to-rail IO capable (but it can get very close to ground due to special design, with top side being typical ~1V shy from a power rail) and due to it there will be early clipping. If the attenuated and filtered PWM signal was given a DC offset ...

I have not seen the edit, I was waiting for a new post lol. I'll do measurements soon. 32X audio output is almost 4Vpp on the cartslot pins, and it clips early, both tips of the sine are flat. There's a 45Hz -3db point high pass filter forming in most MDs (47µF cap in 32X, 75ohm load on most MDs). A...

That is a pretty nice writeup ~

Someone make me a 32X test ROM with same sort of grayscale ramp as seen here : viewtopic.php?f=22&t=2188

And while at it, play a full scale sinewave on both L and R side, I'll get the scope out and measure the levels at various points.

http://www.tmeeco.eu/SMD/Hardware_Inter ... 20Wiki.mht

I have been using that

68K duplicates high and lwo bytes during 8bit writes (i.e $12 is $1212 on the bus). Reads are aways 16bit and CPU internally chooses which half to use depending on address.

Computer composhit output would look nothing like the MD output (i.e near complete lack of various artifacts) and you still have the problem of non-linear level ramp that most emulators and tools don't treat right from what I know ( http://gendev.spritesmind.net/forum/viewtopic.php?f=22&t=2188 ). Th...

I haven't had any issues by doing a shorter than 192 cycle reset, but I always explicitly zero out all the YM registers and it seems internal state is also fine.

68K User manual suggests it is based on bus cycles rather than instruction cycles, I got the impression you can get the bus while an instruction is still halfway done. The processor asserts BG as soon as possible. Normally, this process immediately follows internal synchronization, except when the p...

There's 16 or 18 access slots spread around one line during rendering, depending on 256 or 320 pixel mode, each capable of accepting one byte so 16 or 18 bytes are possible to transfer in best case during a line. 4x 68K cycles is 3.5 pixels, these access slots come in triplets that are 16 pixels apa...