Statistics: Posted by awye — Tue Feb 27, 2024 6:32 am
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Statistics: Posted by Matt Grum — Mon Feb 19, 2024 1:37 pm
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Statistics: Posted by Nemesis — Fri Feb 16, 2024 12:08 am
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Statistics: Posted by Matt Grum — Wed Feb 07, 2024 3:15 pm
Statistics: Posted by Nemesis — Sat Feb 03, 2024 2:15 am
CODE:
a - ALU Input from "address" bus in Execution Unitd - ALU Input from "data" bus in Execution Unitr - ALU Output (result), stored in the ALU Output registerx - Arithmetic carry (X flag from CCR)c - Standard carry (C flag from CCR)' - Compliment of preceding source (Bitwise NOT)^ - Bitwise ANDv - Bitwise OR1 - The constant "1"0 - The constant "0"
CODE:
cm - Carry signal generated from the most significant bit of the ALUcm' - Binary NOT of cmmsb - Most significant bit of the ALU resultabd[0] - Bit 0 of from "address bus data" input value0 - The constant "0"
Statistics: Posted by Nemesis — Sat Feb 03, 2024 1:21 am
CODE:
AOB(H/L) - Address Output Buffer, a 32-bit latched register which stores the address value to output over the external address bus. Shown outside the execution unit as AOBH/AOBL above, but actually physically embedded within it like other registers. ["Memory address register" in Gigasoft analysis]AT(H/L) = Address Temporary register ["immediate register" in Gigasoft analysis]DT(H/L) = Data Temporary register ["Register B" in Gigasoft analysis]PC(H/L) = Program Counter registerRF(H/L)' = SSPRF(H/L) = USPRE(H/L) = A6RD(H/L) = A5RC(H/L) = A4RB(H/L) = A3RA(H/L) = A2R9(H/L) = A1R8(H/L) = A0R7(H/blank) = D7R6(H/blank) = D6R5(H/blank) = D5R4(H/blank) = D4R3(H/blank) = D3R2(H/blank) = D2R1(H/blank) = D1R0(H/blank) = D0where (H = Upper 16 bits (high), L or blank = Lower 16 bits (low))
CODE:
AUH Output - A latched (registered) 16-bit output from AUH (read-only, only AUH can modify) ["Register A" high 16 bits in Gigasoft analysis]AUL Output - A latched (registered) 16-bit output from AUL (read-only, only AUL can modify) ["Register A" low 16 bits in Gigasoft analysis]ALU Output - A latched (registered) 16-bit output from ALU (read-only, only ALU can modify) ["Register C" in Gigasoft analysis]ALUB - ALU Buffer register - A 16-bit input register to ALU (write-only, only ALU can read) ["Register E" in Gigasoft analysis]ALUE - ALU Extension register - A 16-bit register that can be generally read and written, but also acts as a special shift register for the ALU. ["Register G" in Gigasoft analysis]DCR - DeCodeR, A latched 4-bit to 16-bit decoder register, takes a 4-bit input and outputs "1" on exactly one of the 16-bit data lines according to the value (IE, 0000 -> 0000000000000001, 0001 -> 0000000000000010, 0010 -> 0000000000000011, etc) ["Bit selection register (BIT#)" for input, "Selected bit (BIT)" for output on Gigasoft analysis]DOB - Data Output Buffer, a 16-bit latched register which stores the value to output over the external data bus. ["Output Register" in Gigasoft analysis]DBIN - Data Bus Input Buffer, a 16-bit latched register which stores the last data value read from the external data bus. ["Register D" in Gigasoft analysis]FTU - Field Translation Unit, a 16-bit latched register which serves as an I/O buffer for reading/writing content stored in other regions of the processor, such as the status register, writing a trap vector to trigger an exception (eg, divide by zero), or extracting bits from the IRD register.PREN - PRiority ENcoder, a 16-bit register which takes a MOVEM register bitmask as an input, and outputs a 4-bit register number representing the internal register number of the next register with a bit set. [[MOVEM register list (List) / next bit in register list in Gigasoft analysis]
CODE:
IRC/IR/IRD - As described in the last post, these 16-bit registers make up the instruction prefetch and decode pipeline. IRC and IR are physically attached to the bottom of the execution unit, but aren't really within it. IRD is located elsewhere.SR - Status Register, as described in the 68000 User's Manual. Contains condition code flags, interrupt mask, supervisor state, and trace mode flags. This isn't a complete 16-bit register, it's stored as a series of latched bits in different regions of the processor.INL - 3-bit pending interrupt levelTPEND - Bit flag indicating trace pending when the current macroinstruction completes
CODE:
____________________________________ | < | || au --> db --> aob,au,pc | irix | mmrw3| +2 --> au |--------|| | dbi || |--------|| | x || |--------|| | dxdy ||___________________________|________|| 213 | b | b |\------------------------------------/ ____________________________________ | > | || edb --> dbin,irc | frix || (ir) --> ird |--------|| | a1 || |--------|| | x || |--------|| | ||___________________________|________|| 26 | mmrw3 | mmrw3 |\------------------------------------/
CODE:
abbreviation | meaning------------------------------------------------------------------------------------------rx | register (data or address) designated by Rx field in macroinstruction rxa | address register designated by Rx field in macroinstruciton rxd | data register designated by Rx field in macroinstruction rxh | upper half (16 most significant bits) of register (data or address) designated by Rx field in macroinstruction rxl | lower half (16 least significant bits) of register (data or address) designated by Rx field in macroinstruction rxdl | lower half (16 least significant bits) of data register designated by Rx field in macroinstructionry | register (data or address) designated by Ry field in macroinstruction rya | address register designated by Ry field in macroinstruciton ryd | data register designated by Ry field in macroinstruction ryh | upper half (16 most significant bits) of register (data or address) designated by Ry field in macroinstruction ryl | lower half (16 least significant bits) of register (data or address) designated by Ry field in macroinstruction rydl | lower half (16 least significant bits) of data register designated by Ry field in macroinstructionrz | register (data or address) designated by 4-bit field of second word of macro-instructions using indexed addressing for specifying register to be used as the index rzl | lower half (16 least significant bits) of register described immediately abovedb | DATA BUS (including high, low and data sections) dbh | DATA BUS (high section only) dbl | DATA BUS (low section only) dbd | DATA BUS (data section only) db* | DATA BUS (at least data section)dbe | sign extend sign bit onto high section of DATA BUSedb | external data busdbin | data bus input buffer (including a latch) coupled to external data bus dbinh | upper byte (8 most significant bits) of data bus input buffer dbinl | lower byte (8 least significant bits) of data bus input bufferdob | data bus output buffer coupled to external data bus dobh | upper byte (8 most significant bits) of data bus output buffer dobl | lower byte (8 least significant bits) of data bus output bufferab | ADDRESS BUS (including high, low and data sections) abh | ADDRESS BUS (high section only) abl | ADDRESS BUS (low section only) abd | ADDRESS BUS (data section only) ab* | ADDRESS BUS (at least data section)abe | sign extend sign bit onto high section of ADDRESS BUSaob | address bus output buffer coupled to external address bus* | ADDRESS BUS (high, low and data sections) or alternatively DATA BUS (high, low and data sections)*e | sign extend sign bit onto high section of ADDRESS BUS or alternatively onto high section of DATA BUSpsw | program status word which stores condition codes, interrupt level, trace mode bit, supervisor mode bitpsws | supervisor mode bit in the program status wordssw | special word which monitors status of current microinstruction; accessed in event of address error or bus error to aid processor in recovery from errorat | temporary address register ath | upper half (16 most significant bits) of temporary address register atl | lower half (16 least significant bits) of temporary address registersp | user or supervisor stack pointer sph | upper half (16 most significant bits) of user or supervisor stack pointer spl | lower half (16 least significant bits) of user or supervisor stack pointerpc | program counter register pch | upper half (16 most significant bits) of program counter register pcl | lower half (16 least significant bits) of program counter registerdcr | decoder in data section of execution unit which is used for bit manipulation'reset pren' | used during instruction which specifies access to multiple registers in order to advance encoder to the address of the next register to be accessedftu | field translation unit'idle wait' | no transfers occur during this microcycletpend | a one-bit latch which indicates whether the current macroinstruction should implement a trace upon completion ot the macroinstructioninl | latch which stores the interrupt level of the interrupting device upon recognition of an interrupt for subsequent transfer into program status wordtrap | stores vector which can be supplied to field translate unit for addressing a trap routine in event of trap condition (e.g. divide-dy-zero)corf | correction factor for decimal arithmetic which can be provided to ALU'sr c-alu-alue' | shift right used in multiply operation; carry bit coupled to msb of ALU; lsb of ALU coupled to msb of ALUE
CODE:
abbreviation | meaning------------------------------------------------------------------------------------------au | AUH (Arithmetic Unit High) and AUL (Arithmetic Unit Low) working together on a 32-bit valuealu | ALU (Arithmetic Logic Unit) working on a 16-bit valueirc | Instruction Register Capture register, top of prefetch pipeline.ir | Instruction Register, next macroinstruction to execute.ird | Instruction Register Delay register, current macroinstruction being executed.alub | ALU Buffer registeralue | ALU Extension register
CODE:
au --> db --> aob,au,pc+2 --> au
CODE:
<source> --> <targetList>: Transfer data from <source> into <targetList><source> --> <bus> --> <targetList>: Transfer data from <source> into <targetList> via <bus><keyword>: Special keyword such as 'reset pren' or 'idle wait', defined above.where <targetList> is a comma separated list of one or more targets, such as "aob,au,sp".
CODE:
// Transfer the 32-bit AUH/AUL contents to aob (address bus output buffer) and pc (program counter) via db (data bus high/low/data)// Additionally, feed the same value back into AUH/AUL as one input.au --> db --> aob,au,pc// Feed the constant +2 into AUH/AUL as another input+2 --> au
CODE:
// Transfer the contents of edb (external data bus) into dbin (data bus input buffer) and irc (instruction register capture).// This is pulling in our prefetched 16-bit value which follows the next instruction after this one. It may or may not be a macroinstruction.edb --> dbin,irc// Load the next instruction being decoded into IRD to make it the "current" instruction(ir) --> ird
Statistics: Posted by Nemesis — Thu Feb 01, 2024 8:30 am